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| PIC24FJ256DA210 Family Data Sheet 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG) 2010 Microchip Technology Inc. DS39969B Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-235-9 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39969B-page 2 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG) Graphics Controller Features: * Three Graphics Hardware Accelerators to Facilitate Rendering of Block Copying, Text and Unpacking of Compressed Data * Color Look-up Table (CLUT) with Maximum of 256 Entries * 1/2/4/8/16 bits-per-pixel (bpp) Color Depth Set at Run Time * Display Resolution Programmable According to Frame Buffer: - Supports direct access to external memory on devices with EPMP Peripheral Features: * Enhanced Parallel Master Port/Parallel Slave Port (EPMP/PSP), 100-pin devices only: - Direct access from CPU with an Extended Data Space (EDS) interface - 4, 8 and 16-bit wide data bus - Up to 23 programmable address lines - Up to 2 chip select lines - Up to 2 Acknowledgement lines (one per chip select) - Programmable address/data multiplexing - Programmable address and data Wait states - Programmable polarity on control signals * Peripheral Pin Select: - Up to 44 available pins (100-pin devices) * Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) * Three I2CTM modules Supporting Multi-Master/Slave modes and 7-Bit/10-Bit Addressing * Four UART modules: - Supports RS-485, RS-232, LIN/J2602 protocols and IrDA(R) * Five 16-Bit Timers/Counters with Programmable Prescaler * Nine 16-Bit Capture Inputs, each with a Dedicated Time Base * Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base * Hardware Real-Time Clock and Calendar (RTCC) * Enhanced Programmable Cyclic Redundancy Check (CRC) Generator * Up to 5 External Interrupt Sources - Resolution supported is up to 480x272 @ 60 Hz, 16 bpp; 640x480 @ 30 Hz, 16 bpp or 640x480 @ 60 Hz, 8 bpp * Supports Various Display Interfaces: - 4/8/16-bit Monochrome STN - 4/8/16-bit Color STN - 9/12/18/24-bit Color TFT (18 and 24-bit displays are connected as 16-bit, 5-6-5 RGB color format) Universal Serial Bus Features: * USB v2.0 On-The-Go (OTG) Compliant * Dual Role Capable - Can act as either Host or Peripheral * Low-Speed (1.5 Mbps) and Full-Speed (12 Mbps) USB Operation in Host mode * Full-Speed USB Operation in Device mode * High-Precision PLL for USB * Supports up to 32 Endpoints (16 bidirectional): - USB module can use the internal RAM location from 0x800 to 0xFFFF as USB endpoint buffers * On-Chip USB Transceiver with Interface for Off-Chip Transceiver * Supports Control, Interrupt, Isochronous and Bulk Transfers * On-Chip Pull-up and Pull-Down Resistors Program Memory (bytes) Graphics Controller Y Y Y Y Y Y Y Y Remappable Peripherals 10-Bit A/D (ch) SRAM (bytes) Comparators UART w/IrDA(R) EPMP/PSP 16-Bit Timers Remappable Pins IC/OC PWM PIC24FJ128DA106 PIC24FJ256DA106 PIC24FJ128DA110 PIC24FJ256DA110 PIC24FJ128DA206 PIC24FJ256DA206 PIC24FJ128DA210 PIC24FJ256DA210 64 64 100/121 100/121 64 64 100/121 100/121 128K 256K 128K 256K 128K 256K 128K 256K 24K 24K 24K 24K 96K 96K 96K 96K 29 29 44 44 29 29 44 44 5 5 5 5 5 5 5 5 9/9 9/9 9/9 9/9 9/9 9/9 9/9 9/9 4 4 4 4 4 4 4 4 SPI PIC24FJ Device 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 16 16 24 24 16 16 24 24 3 3 3 3 3 3 3 3 Y Y Y Y Y Y Y Y N N Y Y N N Y Y Y Y Y Y Y Y Y Y 2010 Microchip Technology Inc. DS39969B-page 3 USB OTG Y Y Y Y Y Y Y Y CTMU RTCC I2CTM Pins PIC24FJ256DA210 FAMILY High-Performance CPU Modified Harvard Architecture Up to 16 MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider 16 x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes * Linear Program Memory Addressing, up to 12 Mbytes * Data Memory Addressing, up to 16 Mbytes: - 2K SFR space - 30K linear data memory - 66K extended data memory - Remaining (from 16 Mbytes) memory (external) can be accessed using extended data Memory (EDS) and EPMP (EDS is divided into 32-Kbyte pages) * Two Address Generation Units for Separate Read and Write Addressing of Data Memory * * * * * * * Analog Features: * 10-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Operation is possible in Sleep mode - Band gap reference input feature * Three Analog Comparators with Programmable Input/Output Configuration * Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches - Minimum time measurement setting at 100 ps * Available LVD Interrupt VLVD Level Special Microcontroller Features: * Operating Voltage Range of 2.2V to 3.6V * 5.5V Tolerant Input (digital pins only) * Configurable Open-Drain Outputs on Digital I/O Ports * High-Current Sink/Source (18 mA/18 mA) on all I/O Ports * Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up * Fail-Safe Clock Monitor (FSCM) Operation: - Detects clock failure and switches to on-chip, FRC oscillator * On-Chip LDO Regulator * Power-on Reset (POR) and Oscillator Start-up Timer (OST) * Brown-out Reset (BOR) * Flexible Watchdog Timer (WDT) with On-Chip Low-Power RC Oscillator for Reliable Operation * In-Circuit Serial ProgrammingTM (ICSPTM) and In-Circuit Debug (ICD) via 2 Pins * JTAG Boundary Scan Support * Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Self-reprogrammable under software control - Write protection option for Configuration Words Power Management: * On-Chip Voltage Regulator of 1.8V * Switch between Clock Sources in Real Time * Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up * Run Mode: 800 A/MIPS, 3.3V Typical * Sleep mode Current Down to 20 A, 3.3V Typical * Standby Current with 32 kHz Oscillator: 22 A, 3.3V Typical DS39969B-page 4 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Pin Diagram (64-Pin TQFP/QFN) HSYNC/CN62/RE4 GD3/CN61/RE3 GD2/CN60/RE2 GD1/CN59/RE1 GD0/CN58/RE0 GD11/VCMPST2/SESSVLD/CN69/RF1 GD10/VBUSST/VCMPST1/VBUSVLD/CN68/RF0 ENVREG VCAP C3INA/SESSEND/CN16/RD7 C3INB/CN15/RD6 RP20/GPWR/CN14/RD5 RP25/GCLK/CN13/RD4 RP22/GEN/CN52/RD3 DPH/RP23/CN51/RD2 VCPCON/RP24/GD9/VBUSCHG/CN50/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSYNC/CN63/RE5 GD12/SCL3/CN64/RE6 GD13/SDA3/CN65/RE7 C1IND/RP21/CN8/RG6 C1INC/RP26/CN9/RG7 C2IND/RP19/GD14/CN10/RG8 MCLR C2INC/RP27/GD15/CN11/RG9 VSS (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/ RC14 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 RP12/GD7/CN56/RD11 SCL1/RP3/GD6/CN55/RD10 DPLN/SDA1/RP4/GD8/CN54/RD9 RTCC/DMLN/RP2/CN53/RD8 VSS(1) OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD D+/CN83/RG2 D-/CN84/RG3 VUSB VBUS/RF7 RP16/USBID/CN71/RF3 PIC24FJXXXDAX06 VDD PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 PGEC1/AN1/VREF-/RP1/CN3/RB1 PGED1/AN0/VREF+/RP0/CN2/RB0 Note 1: Legend: The back pad on QFN devices should be connected to VSS. RPn and RPIn represents remappable peripheral pins. Shaded pins indicate pins that are tolerant to up to +5.5V. 2010 Microchip Technology Inc. PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/CN25/RB7 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/CN27/RB9 TMS/CVREF/AN10/CN28/RB10 TDO/AN11/CN29/RB11 VSS(1) VDD TCK/AN12/CTEDG2/CN30/RB12 TDI/AN13CTEDG1/CN31/RB13 AN14/CTPLS/RP14/CN32/RB14 AN15/RP29/REFO/CN12/RB15 SDA2/RP10/GD4/CN17/GD4/RF4 SCL2/RP17/GD5/CN18/RF5 DS39969B-page 5 PIC24FJ256DA210 FAMILY TABLE 1: Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Legend: VSYNC/CN63/RE5 GD12/SCL3/CN64/RE6 GD13/SDA3/CN65/RE7 C1IND/RP21/CN8/RG6 C1INC/RP26/CN9/RG7 C2IND/RP19/GD14/CN10/RG8 MCLR C2INC/RP27/GD15/CN11/RG9 VSS VDD PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 PGEC1/AN1/VREF-/RP1/CN3/RB1 PGED1/AN0/VREF+/RP0/CN2/RB0 PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/CN25/RB7 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/CN27/RB9 TMS/CVREF/AN10/CN28/RB10 TDO/AN11/CN29/RB11 VSS VDD TCK/AN12/CTEDG2/CN30/RB12 TDI/AN13/CTEDG1/CN31/RB13 AN14/CTPLS/RP14/CN32/RB14 AN15/RP29/REFO/CN12/RB15 SDA2/RP10/GD4/CN17/RF4 SCL2/RP17/GD5/CN18/RF5 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN DEVICES Function Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RP16/USBID/CN71/RF3 VBUS/RF7 VUSB D-/CN84/RG3 D+/CN83/RG2 VDD OSCI/CLKI/CN23/RC12 OSCO/CLKO/CN22/RC15 VSS RTCC/DMLN/RP2/CN53/RD8 DPLN/SDA1/RP4/GD8/CN54/RD9 SCL1/RP3/GD6/CN55/RD10 RP12/GD7/CN56/RD11 DMH/RP11/INT0/CN49/RD0 SOSCI/C3IND/CN1/RC13 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 VCPCON/RP24/GD9/VBUSCHG/CN50/RD1 DPH/RP23/CN51/RD2 RP22/GEN/CN52/RD3 RP25/GCLK/CN13/RD4 RP20/GPWR/CN14/RD5 C3INB/CN15/RD6 C3INA/SESSEND/CN16/RD7 VCAP ENVREG GD10/VBUSST/VCMPST1/VBUSVLD/CN68/RF0 GD11/VCMPST2/SESSVLD/CN69/RF1 GD0/CN58/RE0 GD1/CN59/RE1 GD2/CN60/RE2 GD3/CN61/RE3 HSYNC/CN62/RE4 Function RPn and RPIn represent remappable pins for Peripheral Pin Select functions. DS39969B-page 6 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Pin Diagram (100-Pin TQFP) PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 HSYNC/CN80/RG13 VSYNC/CN79/RG12 PMA16/CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 AN22/PMA17/CN40/RA7 AN23/GEN/CN39/RA6 PMD8/CN77/RG0 PMD9/CN78/RG1 VCMPST2/SESSVLD/PMD10/CN69/RF1 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 ENVREG VCAP C3INA/SESSEND/PMD15/CN16/RD7 C3INB/PMD14/CN15/RD6 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 PMD13/CN19/RD13 RPI42/PMD12/CN57/RD12 RP22/PMBE0/CN52/RD3 DPH/RP23/GD11/PMACK1/CN51/RD2 VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GCLK/CN82/RG15 VDD PMD5/CN63/RE5 SCL3/PMD6/CN64/RE6 SDA3/PMD7/CN65/RE7 RPI38/GD0/CN45/RC1 RPI39/GD8/CN46/RC2 RPI40/GD1/CN47/RC3 AN16/RPI41/PMCS2/PMA22/CN48/RC4 AN17/C1IND/RP21/PMA5/PMA18/CN8/ RG6 AN18/C1INC/RP26/PMA4/PMA20/CN9/RG7 AN19/C2IND/RP19/PMA3/PMA21/CN10/RG8 MCLR AN20/C2INC/RP27/PMA2/CN11/RG9 VSS VDD TMS/CN33/RA0 RPI33/PMCS1/CN66/RE8 AN21/RPI34/PMA19/CN67/RE9 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 AN3/C2INA/GD5/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 PGEC1/AN1/VREF-/RP1/CN3/RB1 PGED1/AN0/VREF+/RP0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 PIC24FJXXXDAX10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/SCLKI/TICK/C3INC/ RPI37/CN0/RC14 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 RP12/PMA14/PMCS1/CN56/RD11 RP3/PMA15/PMCS2/CN55/ RD10 DPLN/RP4/GD10/PMACK2/CN54/ RD9 DMLN/RTCC/RP2/CN53/RD8 SDA1/RPI35/PMBE1/CN44/ RA15 SCL1/RPI36/ PMA22/PMCS2/ CN43/RA14 VSS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD TDO/CN38/RA5 TDI/PMA21/PMA3/CN37/RA4 SDA2/PMA20/PMA4/CN36/RA3 SCL2/CN35/RA2 D+/CN83/RG2 D-/CN84/RG3 VUSB VBUS/CN73/RF7 RP15/GD9/CN74/RF8 RP30/GD3/CN70/RF2 RP16/USBID/CN71/RF3 AVDD AVSS AN8/RP8/GD12/CN26/RB8 GD13/AN9/RP9/GD13/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/GD2/CN76/RF13 RPI32/PMA18/PMA5/CN75/RF12 AN12/PMA11/CTEDG2/CN30/RB12 AN13/PMA10/CTEDG1/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/REFO/RP29/PMA0/CN12/RB15 Legend: RPn and RPIn represent remappable peripheral pins. Shaded pins indicate pins that are tolerant to up to +5.5V. 2010 Microchip Technology Inc. PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 VREF-/PMA7/CN41/RA9 VREF+/PMA6/CN42/RA10 VSS VDD RPI43/GD14/CN20/RD14 RP5/GD15/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS39969B-page 7 PIC24FJ256DA210 FAMILY TABLE 2: Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Legend: Note 1: 2: 3: GCLK/CN82/RG15 VDD PMD5/CN63/RE5 SCL3/PMD6/CN64/RE6 SDA3/PMD7/CN65/RE7 RPI38/GD0/CN45/RC1 RPI39/GD8/CN46/RC2 RPI40/GD1/CN47/RC3 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 AN17/C1IND/RP21/PMA5/PMA18(2)/CN8/RG6 AN18/C1INC/RP26/PMA4/PMA20(2)/CN9/RG7 AN19/C2IND/RP19/PMA3/PMA21(2)/CN10/RG8 MCLR AN20/C2INC/RP27/PMA2/CN11/RG9 VSS VDD TMS/CN33/RA0 RPI33/PMCS1/CN66/RE8 AN21/RPI34/PMA19/CN67/RE9 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 AN3/C2INA/GD5/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 VREF-/PMA7/CN41/RA9 VREF+/PMA6/CN42/RA10 AVDD AVSS AN8/RP8/GD12/CN26/RB8 AN9/RP9/GD13/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/GD2/CN76/RF13 RPI32/PMA18/PMA5(2)/CN75/RF12 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Function Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function AN12/PMA11/CTEDG2/CN30/RB12 AN13/PMA10/CTEDG1/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/REFO/RP29/PMA0/CN12/RB15 VSS VDD RPI43/GD14/CN20/RD14 RP5/GD15/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 RP16/USBID/CN71/RF3 RP30/GD3/CN70/RF2 RP15/GD9/CN74/RF8 VBUS/CN73/RF7 VUSB D-/CN84/RG3 D+/CN83/RG2 SCL2/CN35/RA2 SDA2/PMA20/PMA4(2)/CN36/RA3 TDI/PMA21/PMA3(2)/CN37/RA4 TDO/CN38/RA5 VDD OSCI/CLKI/CN23/RC12 OSCO/CLKO/CN22/RC15 VSS SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 SDA1/RPI35/PMBE1/CN44/RA15 DMLN/RTCC/RP2/CN53/RD8 DPLN/RP4/GD10/PMACK2/CN54/RD9 RP3/PMA15/PMCS2(3)/CN55/RD10 RP12/PMA14/PMCS1(3)/CN56/RD11 DMH/RP11/INT0/CN49/RD0 SOSCI/C3IND/CN1/RC13 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 VSS VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 DPH/RP23/GD11/PMACK1/CN51/RD2 RP22/PMBE0/CN52/RD3 RPI42/PMD12/CN57/RD12 PMD13/CN19/RD13 RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. Pin assignment for PMCSx when CSF<1:0> is not equal to `00'. DS39969B-page 8 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 2: Pin 81 82 83 84 85 86 87 88 89 90 Legend: Note 1: 2: 3: RP25/PMWR/CN13/RD4 RP20/PMRD/CN14/RD5 C3INB/PMD14/CN15/RD6 C3INA/SESSEND/PMD15/CN16/RD7 VCAP ENVREG VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 VCMPST2/SESSVLD/PMD10/CN69/RF1 PMD9/CN78/RG1 PMD8/CN77/RG0 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Function Pin 91 92 93 94 95 96 97 98 99 100 AN23/GEN/CN39/RA6 AN22/PMA17/CN40/RA7 PMD0/CN58/RE0 PMD1/CN59/RE1 PMA16/CN81/RG14 VSYNC/CN79/RG12 HSYNC/CN80/RG13 PMD2/CN60/RE2 PMD3/CN61/RE3 PMD4/CN62/RE4 Function RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. Pin assignment for PMCSx when CSF<1:0> is not equal to `00'. 2010 Microchip Technology Inc. DS39969B-page 9 PIC24FJ256DA210 FAMILY Pin Diagram - Top View (121-Pin BGA)(1) 1 2 3 4 5 6 7 8 9 10 11 A RE4 RE3 HSYNC/ RG13 RE2 RE0 RG0 RF1 ENVREG N/C RD12 GD11/ RD2 VSS GD7/ RD1 RC14 B N/C GCLK/ RG15 VDD RE1 RA7 RF0 VCAP RD5 RD3 C RE6 VSYNC/ RG12 RE5 RG14 GEN/ RA6 VSS N/C RD7 RD4 VDD RC13 RD11 D GD0/ RC1 RC4 RE7 VSS N/C RD6 RD13 RD0 n/c RD10 E GD1/ RC3 RG8 RG6 GD8/ RC2 RG7 VDD RG1 N/C RA15 RD8 GD10/ RD9 VSS RA14 F MCLR RG9 VSS n/c N/C VDD OSCI/ RC12 RA5 OSCO/ RC15 RA4 G RE8 RE9 RA0 N/C VDD VSS VSS N/C RA3 H PGEC3/ PGED3/ GD4/RB4 RB5 GD5/ RB3 PGEC1/ RB1 PGEC2/ RB6 GD6/ RB2 PGED1/ RB0 RA9 VSS VDD N/C VDD n/c VBUS/ RF7 N/C VUSB D+/RG2 RA2 J PGED2/RB7 AVDD GPWR RB11 RA1 RB12 N/C GD9/RF8 D-/RG3 K RA10 GD12/ RB8 GD13/ RB9 N/C RF12 RB14 VDD GD15/ RD15 GD14/ RD14 USBID/ RF3 RF4 GD3/ RF2 RF5 L AVSS RB10 GD2/ RF13 RB13 RB15 Note 1: Legend: See Table 3 for complete functional pinout descriptions. RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Shaded pins indicate pins tolerant to up to +5.5V. DS39969B-page 10 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 3: Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 Legend: Note 1: 2: 3: PMD4/CN62/RE4 PMD3/CN61/RE3 HSYNC/CN80/RG13 PMD0/CN58/RE0 PMD8/CN77/RG0 VCMPST2/SESSVLD/PMD10/CN69/RF1 ENVREG N/C RPI42/PMD12/CN57/RD12 DPH/RP23/GD11/PMACK1/CN51/RD2 VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 N/C GCLK/CN82/RG15 PMD2/CN60/RE2 PMD1/CN59/RE1 AN22/PMA17/CN40/RA7 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 VCAP RP20/PMRD/CN14/RD5 RP22/PMBE0/CN52/RD3 VSS SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 SCL3/PMD6/CN64/RE6 VDD VSYNC/CN79/RG12 PMA16/CN81/RG14 AN23/GEN/CN39/RA6 N/C C3INA/SESSEND/PMD15/CN16/RD7 RP25/PMWR/CN13/RD4 VDD SOSCI/C3IND/CN1/RC13 RP12/PMA14/PMCS1(3)/CN56/RD11 RPI38/GD0/CN45/RC1 SDA3/PMD7/CN65/RE7 PMD5/CN63/RE5 VSS VSS N/C C3INB/PMD14/CN15/RD6 PMD13/CN19/RD13 DMH/RP11/INT0/CN49/RD0 N/C RP3/PMA15/PMCS2(3)/CN55/RD10 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 RPI40/GD1/CN47/RC3 AN17/C1IND/RP21/PMA5/PMA18(2)/CN8/RG6 RPI39/GD8/CN46/RC2 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES Function Pin E5 E6 E7 E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 VDD PMD9/CN78/RG1 N/C SDA1/RPI35/PMBE1/CN44/RA15 DMLN/RTCC/RP2/CN53/RD8 DPLN/RP4/GD10/PMACK2/CN54/RD9 SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 MCLR AN19/C2IND/RP19/PMA3/PMA21(2)/CN10/RG8 AN20/C2INC/RP27/PMA2/CN11/RG9 AN18/C1INC/RP26/PMA4/PMA20(2)/CN9/RG7 VSS N/C N/C VDD OSCI/CLKI/CN23/RC12 VSS OSCO/CLKO/CN22/RC15 RPI33/PMCS1/CN66/RE8 AN21/RPI34/PMA19/CN67/RE9 TMS/CN33/RA0 N/C VDD VSS VSS N/C TDO/CN38/RA5 SDA2/PMA20/PMA4(2)/CN36/RA3 TDI/PMA21/PMA3(2)/CN37/RA4 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 VSS VDD N/C VDD N/C VBUS/CN73/RF7 VUSB D+/CN83/RG2 SCL2/CN35/RA2 AN3/C2INA/GD5/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 AVDD AN11/PMA12/CN29/RB11 TCK/CN34/RA1 AN12/PMA11/CTEDG2/CN30/RB12 N/C Function RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. Pin assignment for PMCSx when CSF<1:0> is not equal to `00'. 2010 Microchip Technology Inc. DS39969B-page 11 PIC24FJ256DA210 FAMILY TABLE 3: Pin J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 Legend: Note 1: 2: 3: N/C RP15/GD9/CN74/RF8 D-/CN84/RG3 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 VREF+(1)/PMA6/CN42/RA10 AN8/RP8/GD12/CN26/RB8 N/C RPI32/PMA18/PMA5(2)/CN75/RF12 AN14/CTPLS/RP14/PMA1/CN32/RB14 VDD RP5/GD15/CN21/RD15 RP16/USBID/CN71/RF3 RP30/GD3/CN70/RF2 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES Function Pin L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 -- -- -- Function PGEC2/AN6/RP6/CN24/RB6 VREF-(1)/PMA7/CN41/RA9 AVSS AN9/RP9/GD13/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 RP31/GD2/CN76/RF13 AN13/PMA10/CTEDG1/CN31/RB13 AN15/REFO/RP29/PMA0/CN12/RB15 RPI43/GD14/CN20/RD14 RP10/PMA9/CN17/RF4 RP17/GD5/PMA8/SCL2/CN18/RF5 -- -- -- RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. Pin assignment for PMCSx when CSF<1:0> is not equal to `00'. DS39969B-page 12 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 33 3.0 CPU ........................................................................................................................................................................................... 39 4.0 Memory Organization ................................................................................................................................................................. 45 5.0 Flash Program Memory.............................................................................................................................................................. 81 6.0 Resets ........................................................................................................................................................................................ 87 7.0 Interrupt Controller ..................................................................................................................................................................... 93 8.0 Oscillator Configuration ............................................................................................................................................................ 141 9.0 Power-Saving Features............................................................................................................................................................ 155 10.0 I/O Ports ................................................................................................................................................................................... 157 11.0 Timer1 ...................................................................................................................................................................................... 189 12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 191 13.0 Input Capture with Dedicated Timers ....................................................................................................................................... 197 14.0 Output Compare with Dedicated Timers .................................................................................................................................. 201 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 211 16.0 Inter-Integrated CircuitTM (I2CTM).............................................................................................................................................. 223 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 231 18.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 239 19.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 273 20.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 285 21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 297 22.0 Graphics Controller Module (GFX)........................................................................................................................................... 305 23.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 325 24.0 Triple Comparator Module........................................................................................................................................................ 335 25.0 Comparator Voltage Reference................................................................................................................................................ 341 26.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 343 27.0 Special Features ...................................................................................................................................................................... 347 28.0 Development Support............................................................................................................................................................... 359 29.0 Instruction Set Summary .......................................................................................................................................................... 363 30.0 Electrical Characteristics .......................................................................................................................................................... 371 31.0 Packaging Information.............................................................................................................................................................. 387 Appendix A: Revision History............................................................................................................................................................. 397 Index ................................................................................................................................................................................................. 399 The Microchip Web Site ..................................................................................................................................................................... 405 Customer Change Notification Service .............................................................................................................................................. 405 Customer Support .............................................................................................................................................................................. 405 Reader Response .............................................................................................................................................................................. 406 Product Identification System ............................................................................................................................................................ 407 2010 Microchip Technology Inc. DS39969B-page 13 PIC24FJ256DA210 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39969B-page 14 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: * PIC24FJ128DA106 * PIC24FJ256DA106 * PIC24FJ128DA110 * PIC24FJ256DA110 * PIC24FJ128DA206 * PIC24FJ256DA206 * PIC24FJ128DA210 * PIC24FJ256DA210 * Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. * Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active with a single instruction in software. The PIC24FJ256DA210 family enhances on the existing line of Microchip`s 16-bit microcontrollers, adding a new Graphics Controller (GFX) module to interface with a graphical LCD display and also adds large data RAM, up to 96 Kbytes. The PIC24FJ256DA210 family allows the CPU to fetch data directly from an external memory device using the EPMP module. 1.1.3 OSCILLATOR OPTIONS AND FEATURES 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE All of the devices in the PIC24FJ256DA210 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: * Two Crystal modes using crystals or ceramic resonators. * Two External Clock modes offering the option of a divide-by-2 clock output. * A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. * A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. * A separate Low-Power Internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC(R) Digital Signal Controllers (DSCs). The PIC24F CPU core offers a wide range of enhancements, such as: * 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces * Linear addressing of up to 12 Mbytes (program space) and 32 Kbytes (data) * A 16-element working register array with built-in software stack support * A 17 x 17 hardware multiplier with support for integer math * Hardware support for 32 by 16-bit division * An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as `C' * Operational performance up to 16 MIPS 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256DA210 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F family is pin compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device. 2010 Microchip Technology Inc. DS39969B-page 15 PIC24FJ256DA210 FAMILY 1.2 Graphics Controller 1.4 Other Special Features With the PIC24FJ256DA210 family of devices, Microchip introduces the Graphics Controller module, which acts as an interface between the CPU (mainly through SFRs) and a display. On-board RAM is provided for display buffer, scratch areas, images and fonts. In some cases, the RAM requirements for the display used exceeds the on-board RAM; external memory connected through EPMP can be used. This module provides acceleration for drawing points, vertical and horizontal lines, rectangles, copying rectangles between different locations on screen, drawing text and decompressing compressed data. * Peripheral Pin Select: The Peripheral Pin Select (PPS) feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. * Communications: The PIC24FJ256DA210 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are three independent I2CTM modules that support both Master and Slave modes of operation. Devices also have, through the PPS feature, four independent UARTs with built-in IrDA(R) encoders/decoders and three SPI modules. * Analog Features: All members of the PIC24FJ256DA210 family include a 10-bit A/D Converter (ADC) module and a triple comparator module. The ADC module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. * CTMU Interface: In addition to their other analog features, members of the PIC24FJ256DA210 family include the CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. * Enhanced Parallel Master/Parallel Slave Port: There are general purpose I/O ports, which can be configured for parallel data communications. In this mode, the device can be master or slave on the communication bus. 4-bit, 8-bit and 16-bit data transfers, with up to 23 external address lines are supported in Master modes. * Real-Time Clock and Calendar: (RTCC) This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. 1.3 USB On-The-Go The USB On-The-Go (USB OTG) module provides on-chip functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB enabled applications on a microcontroller platform. In addition to USB host functionality, PIC24FJ256DA210 family devices provide a true single chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. DS39969B-page 16 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 1.5 Details on Individual Family Members 5. Devices in the PIC24FJ256DA210 family are available in 64-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in seven ways: 1. Flash program memory (128 Kbytes for PIC24FJ128DAXXX devices and 256 Kbytes for PIC24FJ256DAXXX devices). Data memory (24 Kbytes for PIC24FJXXXDA1XX devices, and 96 Kbytes for PIC24FJXXXDA2XX devices). Available I/O pins and ports (52 pins on 6 ports for PIC24FJXXXDAX06 devices and 84 pins on 7 ports for PIC24FJXXXDAX10 devices). Available Interrupt-on-Change Notification (ICN) inputs (52 on PIC24FJXXXDAx06 devices and 84 on PIC24FJXXXDAX10 devices). Available remappable pins (29 pins on PIC24FJXXXDAX06 devices and 44 pins on PIC24FJXXXDAX10 devices). Analog channels for ADC (16 channels for PIC24FJXXXDAX06 devices and 24 channels for PIC24FJxxxDAx10 devices). EPMP module (available in PIC24FJXXXDAX10 devices and not in PIC24FJXXXDAX06 devices). 6. 7. All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. A list of the pin features available on the PIC24FJ256DA210 family devices, sorted by function, is shown in Table 1-1. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. 2. 3. 4. 2010 Microchip Technology Inc. DS39969B-page 17 PIC24FJ256DA210 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256DA210 FAMILY: 64-PIN Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/ NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2CTM Parallel Communications (EPMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Converter (ADC) Module (input channels) Analog Comparators CTMU Interface USB OTG Graphics Controller Resets (and Delays) 4(1) 3(1) 3 No Yes 16 3 Yes Yes Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP and QFN Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 52 128K 44,032 24K 65 (61/4) Ports B, C, D, E, F, G 52 29 (28 I/O, 1 Input only) 256K 87,552 PIC24FJ128DA106 PIC24FJ256DA106 PIC24FJ128DA206 128K 44,032 96K PIC24FJ256DA206 256K 87,552 DC - 32 MHz Instruction Set Packages Note 1: DS39969B-page 18 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256DA210 FAMILY: 100-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2CTM Parallel Communications (EPMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Converter (ADC) Module (input channels) Analog Comparators CTMU Interface USB OTG Graphics Controller Resets (and delays) 4(1) 3(1) 3 Yes Yes 24 3 Yes Yes Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 100-Pin TQFP and 121-Pin BGA Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 84 128K 44,032 24K 66 (62/4) Ports A, B, C, D, E, F, G 84 44 (32 I/O, 12 input only) 256K 87,552 PIC24FJ128DA110 PIC24FJ256DA110 PIC24FJ128DA210 PIC24FJ256DA210 DC - 32 MHz 128K 44,032 96K 256K 87,552 Instruction Set Packages Note 1: 2010 Microchip Technology Inc. DS39969B-page 19 PIC24FJ256DA210 FAMILY FIGURE 1-1: PIC24FJ256DA210 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller Data Bus 16 8 16 16 Data Latch PORTA(1) (12 I/O) EDS and Table Data Access Control Block 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Up to 0x7FFF Address Latch 16 16 Read AGU Write AGU PORTB (16 I/O) 23 Address Latch Program Memory/ Extended Data Space Data Latch PORTC(1) (8 I/O) Address Bus 24 Inst Latch Inst Register Instruction Decode and Control OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference ENVREG Voltage Regulator Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer LVD & BOR Literal Data EA MUX 16 16 16 PORTD(1) (16 I/O) PORTE(1) Divide Support 17x17 Multiplier 16 x 16 W Reg Array (10 I/O) REFO 16-Bit ALU 16 PORTF(1) (10 I/O) PORTG(1) (12 I/O) VCAP VDD, VSS MCLR Timer1 Timer2/3(2) Timer4/5(2) RTCC 10-Bit ADC Comparators(2) USB OTG EPMP/PSP(3) IC 1-9(2) Note 1: 2: 3: OC/PWM 1-9(2) SPI 1/2/3(2) I2CTM 1/2/3 ICNs(1) UART 1/2/3/4(2) CTMU(2) Graphics Controller Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count. These peripheral I/Os are only accessible through remappable pins. Not available on 64-pin devices (PIC24FJxxxDAx06). DS39969B-page 20 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS Pin Number 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 9 10 11 12 14 19 92 91 30 31 20 21 11 10 22 23 14 12 84 83 74 73 63 64 121-Pin BGA K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 E1 E3 F4 F2 F3 G2 B5 C5 J4 L3 H1 H2 F4 E3 J1 J2 F3 F2 C7 D7 B11 C10 F9 F11 I/O Input Buffer ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA -- -- ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ST -- Positive Supply for Analog modules. Ground Reference for Analog modules. Comparator 1 Input A. Comparator 1 Input B. Comparator 1 Input C. Comparator 1 Input D. Comparator 2 Input A. Comparator 2 Input B. Comparator 2 Input C. Comparator 2 Input D. Comparator 3 Input A. Comparator 3 Input B. Comparator 3 Input C. Comparator 3 Input D. Main Clock Input Connection. System Clock Output. A/D Analog Inputs. Description 64-Pin TQFP/QFN 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 -- -- -- -- -- -- -- -- 19 20 11 12 5 4 13 14 8 6 55 54 48 47 39 40 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AVDD AVSS C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C3INA C3INB C3INC C3IND CLKI CLKO Legend: Note 1: 2: 3: 4: I I I I I I I I I I I I I I I I I I I I I I I I P P I I I I I I I I I I I I I O TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. 2010 Microchip Technology Inc. DS39969B-page 21 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 64 63 26 27 32 33 34 35 41 42 43 17 38 58 59 60 61 91 121-Pin BGA B11 C10 K2 K1 J2 J1 H2 H1 E3 F4 F2 F3 L8 C8 B8 D7 C7 L10 L11 D8 L9 K9 F11 F9 L1 J3 K4 L4 L5 J5 J7 L7 K7 G3 J6 H11 G10 G11 G9 C5 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Interrupt-on-Change Inputs. Description 64-Pin TQFP/QFN 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 -- -- -- 40 39 17 18 21 22 23 24 27 28 29 -- -- -- -- -- -- -- CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN24 CN25 CN26 CN27 CN28 CN29 CN30 CN31 CN32 CN33 CN34 CN35 CN36 CN37 CN38 CN39 Legend: Note 1: 2: 3: 4: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. DS39969B-page 22 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 92 28 29 66 67 6 7 8 9 72 76 77 78 68 69 70 71 79 93 94 98 99 100 3 4 5 18 19 87 88 52 51 54 53 40 39 90 89 96 97 121-Pin BGA B5 L2 K3 E11 E8 D1 E4 E2 E1 D9 A11 A10 B9 E9 E10 D11 C11 A9 A4 B4 B3 A2 A1 D3 C1 D2 G1 G2 B6 A6 K11 K10 H8 J10 K6 L6 A5 E6 C3 A3 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Interrupt-on-Change Inputs. Description 64-Pin TQFP/QFN -- -- -- -- -- -- -- -- -- 46 49 50 51 42 43 44 45 -- 60 61 62 63 64 1 2 3 -- -- 58 59 -- 33 -- -- -- -- -- -- -- -- CN40 CN41 CN42 CN43 CN44 CN45 CN46 CN47 CN48 CN49 CN50 CN51 CN52 CN53 CN54 CN55 CN56 CN57 CN58 CN59 CN60 CN61 CN62 CN63 CN64 CN65 CN66 CN67 CN68 CN69 CN70 CN71 CN73 CN74 CN75 CN76 CN77 CN78 CN79 CN80 Legend: Note 1: 2: 3: 4: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. 2010 Microchip Technology Inc. DS39969B-page 23 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 95 1 57 56 42 41 43 34 57 56 72 68 77 69 86 1 6 8 39 52 21 22 23 76 7 53 69 77 32 33 47 48 91 27 97 72 13 63 64 121-Pin BGA C4 B2 H10 J11 L7 J7 K7 L5 H10 J11 D9 E9 A10 E10 J7 B2 D1 E2 L6 K11 H2 J1 J2 A11 E4 J10 E10 A10 K4 L4 L9 K9 C5 J3 A3 D9 F1 F9 F11 I/O Input Buffer ST ST ST ST ANA ANA -- -- -- -- -- -- -- -- ST -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ST ST ANA ANA Graphics Display Enable Output. Graphics Display Power System Enable. Graphics Display Horizontal Sync Pulse. External Interrupt Input. Master Clear (device Reset) Input. This line is brought low to cause a Reset. Main Oscillator Input Connection. Main Oscillator Output Connection. Graphics Controller Data Output. CTMU External Edge Input 1. CTMU External Edge Input 2. CTMU Pulse Output. Comparator Voltage Reference Output. USB Differential Plus Line (internal transceiver). USB Differential Minus Line (internal transceiver). D- External Pull-up Control Output. D- External Pull-down Control Output. D+ External Pull-up Control Output. D+ External Pull-down Control Output. Voltage Regulator Enable. Graphics Display Pixel Clock. Interrupt-on-Change Inputs. Description 64-Pin TQFP/QFN -- -- 37 36 28 27 29 23 37 36 46 42 50 43 57 52 60 61 62 63 31 32 44 45 43 49 58 59 2 3 6 8 51 53 64 46 7 39 40 CN81 CN82 CN83 CN84 CTEDG1 CTEDG2 CTPLS CVREF D+ DDMH DMLN DPH DPLN ENVREG GCLK GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 GEN GPWR HSYNC INT0 MCLR OSCI OSCO Legend: Note 1: 2: 3: 4: I I I I I I O O I/O I/O O O O O I O O O O O O O O O O O O O O O O O O O O I I I O TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. DS39969B-page 24 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 24 25 26 27 20 21 44 43 14 12, 60(1) 11,59(1) 10,40(1) 29 28 50 49 42 41 35 34 71 70 95 92 40,10 19 59, 11(1) 60,12(1) 66,9(1) 77 69 44 43 14 78 67 71 ,18 70(2),9, 66(1) (3) (1) 64-Pin TQFP/QFN 15 16 17 18 11 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 121-Pin BGA K1 K2 L1 J3 H1 H2 L8 K7 F3 F2, G11(1) F4,G10(1) E3,K6(1) K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 C4 B5 K6,E3 G2 G10, F4(1) G11,F2(1) E11,E1(1) A10 E10 L8 K7 F3 B9 E8 C11 (3) (1) I/O Input Buffer ST ST ST ST ST ST ST ST -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Description PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMA16 PMA17 PMA18 PMA19 PMA20 PMA21 PMA22 PMACK1 PMACK2 PMALL PMALH PMALU PMBE0 PMBE1 PMCS1 PMCS2 Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O I I O O O O O I/O O In-Circuit Debugger/Emulator/ICSPTM Programming Clock 1. In-Circuit Debugger/Emulator/ICSP Programming Data 1. In-Circuit Debugger/Emulator/ICSP Programming Clock 2. In-Circuit Debugger/Emulator/ICSP Programming Data 2. In-Circuit Debugger/Emulator/ICSP Programming Clock 3. In-Circuit Debugger/Emulator/ICSP Programming Data 3. Parallel Master Port Address bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address bits<22:2>. ST/TTL Parallel Master Port Acknowledge Input 1. ST/TTL Parallel Master Port Acknowledge Input 2. -- -- -- -- -- -- Parallel Master Port Lower Address Latch Strobe. Parallel Master Port Higher Address Latch Strobe. Parallel Master Port Upper Address Latch Strobe. Parallel Master Port Byte Enable Strobe 0. Parallel Master Port Byte Enable Strobe 1. ,G1 ST/TTL Parallel Master Port Chip Select Strobe 1. Parallel Master Port Chip Select Strobe 2. D11(2),E1, E11(1) TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. 2010 Microchip Technology Inc. DS39969B-page 25 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 93 94 98 99 100 3 4 5 90 89 88 87 79 80 83 84 82 81 17 38 58 59 60 61 91 92 28 29 66 67 121-Pin BGA A4 B4 B3 A2 A1 D3 C1 D2 A5 E6 A6 B6 A9 D8 D7 C7 B8 C8 G3 J6 H11 G10 G11 G9 C5 B5 L2 K3 E11 E8 I/O Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Read Strobe. ST/TTL Parallel Master Port Write Strobe. ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTA Digital I/O. Parallel Master Port Data bits<15:0>. Description 64-Pin TQFP/QFN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMRD PMWR RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. DS39969B-page 26 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 27 121-Pin BGA K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 D1 E4 E2 E1 F9 C10 B11 F11 J3 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST USB Receive Input (from external transceiver). ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. Description 64-Pin TQFP/QFN 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 -- -- -- -- 39 47 48 40 18 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 RCV Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. 2010 Microchip Technology Inc. DS39969B-page 27 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 44 87 88 52 51 49 50 54 53 40 39 121-Pin BGA D9 A11 A10 B9 C8 B8 D7 C7 E9 E10 D11 C11 A9 D8 L9 K9 A4 B4 B3 A2 A1 D3 C1 D2 G1 G2 L8 B6 A6 K11 K10 L10 L11 H8 J10 K6 L6 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer PORTF Digital I/O. Reference Clock Output. PORTE Digital I/O. PORTD Digital I/O. Description 64-Pin TQFP/QFN 46 49 50 51 52 53 54 55 42 43 44 45 -- -- -- -- 60 61 62 63 64 1 2 3 -- -- 30 58 59 -- 33 31 32 34 -- -- -- RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 REFO RF0 RF1 RF2 RF3 RF4 RF5 RF7 RF8 RF12 RF13 Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. DS39969B-page 28 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 90 89 57 56 10 11 12 14 96 97 95 1 25 24 68 70 69 48 26 27 32 33 49 72 71 23 43 53 51 50 20 12 121-Pin BGA A5 E6 H10 J11 E3 F4 F2 F3 C3 A3 C4 B2 K2 K1 E9 D11 E10 K9 L1 J3 K4 L4 L10 D9 C11 J2 K7 J10 K10 L11 H1 F2 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Remappable Peripheral (input or output). PORTG Digital I/O. Description 64-Pin TQFP/QFN -- -- 37 36 4 5 6 8 -- -- -- -- 16 15 42 44 43 -- 17 18 21 22 31 46 45 14 29 -- 33 32 11 6 RG0 RG1 RG2 RG3 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. 2010 Microchip Technology Inc. DS39969B-page 29 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 82 10 78 77 76 81 11 14 21 44 52 39 40 18 19 67 66 74 6 7 8 9 79 47 68 66 58 4 74 67 59 5 84 88 73 74 74 121-Pin BGA B8 E3 B9 A10 A11 C8 F4 F3 H2 L8 K11 L6 K6 G1 G2 E8 E11 B11 D1 E4 E2 E1 A9 L9 E9 E11 H11 C1 B11 E8 G10 D2 C7 A6 C10 B11 B11 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- I2CTM I2C I2C ANA I2C I2C IC ST ST ANA ANA ST 2 64-Pin TQFP/QFN 53 4 51 50 49 52 5 8 12 30 -- -- -- -- -- -- -- 48 -- -- -- -- -- -- 42 44 32 2 48 43 31 3 55 59 47 48 48 Description RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RPI32 RPI33 RPI34 RPI35 RPI36 RPI37 RPI38 RPI39 RPI40 RPI41 RPI42 RPI43 RTCC SCL1 SCL2 SCL3 SCLKI SDA1 SDA2 SDA3 SESSEND SESSVLD SOSCI SOSCO T1CK Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I O I/O I/O I/O O I/O I/O I/O I I I O I Remappable Peripheral (input or output). Remappable Peripheral (input only). Real-Time Clock Alarm/Seconds Pulse Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C3 Synchronous Serial Clock Input/Output. Secondary Clock Input. I2C1 Data Input/Output. I2C2 Data Input/Output. I2C3 Data Input/Output. USB VBUS Boost Generator, Comparator Input 3. USB VBUS Boost Generator, Comparator Input 2. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Timer1 Clock. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. DS39969B-page 30 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 38 60 61 17 51 21 54 76 20 87 87 85 87 88 76 2, 16, 37, 46, 62 23 22 28, 24(4) 29, 25(4) 15, 36, 45, 65, 75 121-Pin BGA J6 G11 G9 G3 K10 H2 H8 A11 H1 B6 B6 B7 B6 A6 A11 C2, C9, F8, G5, H6, K8, H4, E5 J2 J1 L2, K1(4) K3, K2(4) B10, F5, F10, G6, G7, H3, D4, D5 C3 H9 I/O Input Buffer ST ST -- ST ST -- ANA -- -- ANA ST -- ST ST -- -- JTAG Test Clock Input. JTAG Test Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. USB OTG ID (OTG mode only). USB Output Enable Control (for external transceiver). USB Voltage, Host mode (5V). External USB VBUS Charge Output. USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. USB VBUS Boost Generator, Comparator Input 1. External Filter Capacitor Connection (regulator enabled). USB VBUS Boost Generator, Comparator Input 1. USB VBUS Boost Generator, Comparator Input 2. USB OTG VBUS PWM/Charge Output. Positive Supply for Peripheral Digital Logic and I/O Pins. Description 64-Pin TQFP/QFN 27 28 24 23 33 12 34 49 11 58 58 56 58 59 49 10, 26, 38 TCK TDI TDO TMS USBID USBOEN VBUS VBUSCHG VBUSON VBUSST VBUSVLD VCAP VCMPST1 VCMPST2 VCPCON VDD I I O I I O I O O I I P I I O P VMIO VPIO VREFVREF+ VSS 14 13 15 16 9, 25, 41 I I I I P ST ST ANA ANA -- USB Differential Minus Input/Output (external transceiver). USB Differential Plus Input/Output (external transceiver). A/D and Comparator Reference Voltage (low) Input. A/D and Comparator Reference Voltage (high) Input. Ground Reference for Logic and I/O Pins. VSYNC VUSB Legend: Note 1: 2: 3: 4: 1 35 96 55 O P -- -- Graphics Display Vertical Sync Pulse. USB Voltage (3.3V). TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3<12>) bit is programmed to `0'. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10. The alternate VREF pins selected when the ALTVREF (CW1<5>) bit is programmed to `0'. 2010 Microchip Technology Inc. DS39969B-page 31 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 32 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS Basic Connection Requirements FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) VDD VDD VSS 2.1 Getting started with the PIC24FJ256DA210 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: * All VDD and VSS pins (see Section 2.2 "Power Supply Pins") * All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 "Power Supply Pins") * MCLR pin (see Section 2.3 "Master Clear (MCLR) Pin") * ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24FJ devices only) (see Section 2.4 "Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)") These pins must also be connected if they are being used in the end application: * PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 "External Oscillator Pins") Additionally, the following pins may be required: * VREF+/VREF- pins used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. R1 R2 MCLR (1) (1) (EN/DIS)VREG VCAP/VDDCORE C1 PIC24FXXXX C6(2) VSS VDD VDD C7 C3(2) VSS AVDD AVSS VDD VSS C5(2) C4(2) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic C7: 10 F, 6.3V or greater, tantalum or ceramic R1: 10 k R2: 100 to 470 Note 1: See Section 2.4 "Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)" for explanation of ENVREG/DISVREG pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. 2: The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. DS39969B-page 33 PIC24FJ256DA210 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS 2.3 Master Clear (MCLR) Pin The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: VDD R1 EXAMPLE OF MCLR PIN CONNECTIONS R2 JP C1 MCLR PIC24FXXXX 2.2.2 TANK CAPACITORS Note 1: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS39969B-page 34 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 2.4 Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) This section applies only to PIC24FJ devices with an on-chip voltage regulator. ESR () FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP Note: 10 1 The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground. The particular connection is determined by whether or not the regulator is to be used: * For ENVREG, tie to VDD to enable the regulator, or to ground to disable the regulator * For DISVREG, tie to ground to enable the regulator or to VDD to disable the regulator Refer to Section 27.2 "On-Chip Voltage Regulator" for details on connecting and using the on-chip regulator. When the regulator is enabled, a low-ESR (<5) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD, and must use a capacitor of 10 F connected to ground. The type can be ceramic or tantalum. A suitable example is the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or equivalent. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. The placement of this capacitor should be close to VCAP/VDDCORE. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 30.0 "Electrical Characteristics" for additional information. When the regulator is disabled, the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to Section 30.0 "Electrical Characteristics" for information on VDD and VDDCORE. 0.1 0.01 0.001 0.01 0.1 1 10 100 Frequency (MHz) 1000 10,000 Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25C, 0V DC bias. 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 28.0 "Development Support". 2010 Microchip Technology Inc. DS39969B-page 35 PIC24FJ256DA210 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application's routing and I/O assignments, ensure that adjacent port pins and other signals in close proximity to the oscillator are benign (i.e., free of high frequencies, short rise and fall times and other similar noise). For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849, "Basic PICmicro(R) Oscillator Design" * AN943, "Practical PICmicro(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work" SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-line Layouts: Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS Primary Oscillator C1 C2 OSCI OSCO GND SOSCO Secondary Oscillator Crystal SOSC I Sec Oscillator: C1 Sec Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 GND Oscillator Crystal C1 OSCI DEVICE PINS DS39969B-page 36 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 2.7 Configuration of Analog and Digital Pins During ICSP Operations If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the ADC module, as follows: * For devices with an ADnPCFG register, clear the bits corresponding to the pin(s) to be configured as analog. Do not change any other bits, particularly those corresponding to the PGECx/PGEDx pair, at any time. * For devices with ANSx registers, set the bits corresponding to the pin(s) to be configured as analog. Do not change any other bits, particularly those corresponding to the PGECx/PGEDx pair, at any time. When a Microchip debugger/emulator is used as a programmer, the user application firmware must correctly configure the ADnPCFG or ANSx registers. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic '0', which may affect user application functionality. If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as "digital" pins. Depending on the particular device, this is done by setting all bits in the ADnPCFG register(s), or clearing all bit in the ANSx registers. All PIC24F devices will have either one or more ADnPCFG registers or several ANSx registers (one for each port); no device will have both. Refer to (Section 23.0 "10-Bit High-Speed A/D Converter") for more specific information. The bits in these registers that correspond to the A/D pins that initialized the emulator must not be changed by the user application firmware; otherwise, communication errors will result between the debugger and the device. 2.8 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins and drive the output to logic low. 2010 Microchip Technology Inc. DS39969B-page 37 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 38 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 44. "CPU with Extended Data Space (EDS)" (DS39732). The information in this data sheet supersedes the information in the FRM. The core supports Inherent (no operand), Relative, Literal, Memory Direct Addressing modes along with three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit x 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit x 16-bit or 8-bit x 8-bit, integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 3-1. The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for interrupts and calls. The lower 32 Kbytes of the data space can be accessed linearly. The upper 32 Kbytes of the data space are referred to as extended data space to which the extended data RAM, EPMP memory space or program memory can be mapped. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. 3.1 Programmer's Model The programmer's model for the PIC24F is shown in Figure 3-2. All registers in the programmer's model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 3-1. All registers associated with the programmer's model are memory mapped. 2010 Microchip Technology Inc. DS39969B-page 39 PIC24FJ256DA210 FAMILY FIGURE 3-1: EDS and Table Data Access Control Block Interrupt Controller 8 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Data Bus 16 16 Data Latch Data RAM Up to 0x7FFF Address Latch 16 RAGU WAGU 16 PIC24F CPU CORE BLOCK DIAGRAM 23 Address Latch Program Memory/ Extended Data Space Data Latch 24 Address Bus ROM Latch EA MUX 16 Literal Data 16 Instruction Decode and Control Control Signals to Various Blocks Instruction Reg Hardware Multiplier Divide Support 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules TABLE 3-1: W0 through W15 PC SR SPLIM TBLPAG RCOUNT CORCON DISICNT DSRPAG DSWPAG CPU CORE REGISTERS Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Repeat Loop Counter Register CPU Control Register Disable Interrupt Count Register Data Space Read Page Register Data Space Write Page Register Register(s) Name DS39969B-page 40 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 3-2: PROGRAMMER'S MODEL 15 Divider Working Registers Multiplier Registers W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Frame Pointer Stack Pointer SPLIM 22 PC 7 TBLPAG 9 DSRPAG 8 DSWPAG 15 RCOUNT 15 SRH SRL 0 ALU STATUS Register (SR) 0 0 Data Space Write Page Register Repeat Loop Counter Register 0 Data Space Read Page Register 0 0 0 0 0 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Working/Address Registers 0 -- -- -- -- -- -- -- DC 2 IPL0 RA N OV Z C 1 15 0 -- -- -- -- -- -- -- -- -- -- -- -- IPL3 ------ 13 DISICNT 0 CPU Control Register (CORCON) Disable Interrupt Count Register Registers or bits are shadowed for PUSH.S and POP.S instructions. 2010 Microchip Technology Inc. DS39969B-page 41 PIC24FJ256DA210 FAMILY 3.2 CPU Control Registers SR: ALU STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0, HSC DC bit 8 U-0 -- bit 15 REGISTER 3-1: R/W-0, HSC(1) R/W-0, HSC(1) R/W-0, HSC(1) R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL2(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IPL1(2) IPL0(2) RA N OV Z C bit 0 Unimplemented: Read as `0' DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4th or 8th low-order bit of the result has occurred IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts are disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: ALU Negative bit 1 = Result was negative 0 = Result was not negative (zero or positive) OV: ALU Overflow bit 1 = Overflow occurred for signed (2's complement) arithmetic in this arithmetic operation 0 = No overflow has occurred Z: ALU Zero bit 1 = An operation, which affects the Z bit, has set it at some time in the past 0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result) C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit of the result occurred 0 = No carry out from the Most Significant bit of the result occurred The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. The IPL Status bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: DS39969B-page 42 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 3-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 C = Clearable bit W = Writable bit `1' = Bit is set r = Reserved bit `0' = Bit is cleared U-0 -- U-0 -- U-0 -- R/C-0, HSC IPL3(1) R-1 r U-0 -- U-0 -- bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown U-0 -- CORCON: CPU CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U = Unimplemented bit, read as `0' Unimplemented: Read as `0' IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Reserved: Read as `1' Unimplemented: Read as `0' The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level; see Register 3-1 for bit description. The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. bit 2 bit 1-0 Note 1: 3.3 Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. 3.3.1 MULTIPLIER The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 2010 Microchip Technology Inc. DS39969B-page 43 PIC24FJ256DA210 FAMILY 3.3.2 DIVIDER 3.3.3 MULTI-BIT SHIFT SUPPORT The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided in Table 3-2. The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 3-2: Instruction ASR SL LSR INSTRUCTIONS THAT USE THE SINGLE BIT AND MULTI-BIT SHIFT OPERATION Description Arithmetic shift right source register by one or more bits. Shift left source register by one or more bits. Logical shift right source register by one or more bits. DS39969B-page 44 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows direct access of program memory from the data space during code execution. from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 4.3 "Interfacing Program and Data Memory Spaces". User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ256DA210 family of devices are shown in Figure 4-1. 4.1 Program Memory Space The program address memory space of the PIC24FJ256DA210 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256DA210 FAMILY DEVICES PIC24FJ128DAXXX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (44K instructions) User Memory Space User Flash Program Memory (87K instructions) PIC24FJ256DAXXX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h Flash Config Words 0157FEh 015800h Flash Config Words Unimplemented Read `0' Unimplemented Read `0' 02ABFEh 02AC00h 7FFFFEh 800000h Reserved Configuration Memory Space Reserved Device Config Registers Device Config Registers F7FFFEh F80000h F8000Eh F80010h Reserved Reserved DEVID (2) DEVID (2) FEFFFEh FF0000h FFFFFEh Note: Memory areas are not shown to scale. 2010 Microchip Technology Inc. DS39969B-page 45 PIC24FJ256DA210 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 FLASH CONFIGURATION WORDS The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). Program memory addresses are always word-aligned on the lower word and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. In PIC24FJ256DA210 family devices, the top four words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration register. The addresses of the Flash Configuration Word for devices in the PIC24FJ256DA210 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1. The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words does not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 27.1 "Configuration Bits". 4.1.2 HARD MEMORY VECTORS All PIC24F devices reserve the addresses between 0x00000 and 0x000200 for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 0x000000 with the actual address for the start of code at 0x000002. PIC24F devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 7.1 "Interrupt Vector Table". TABLE 4-1: FLASH CONFIGURATION WORDS FOR PIC24FJ256DA210 FAMILY DEVICES Program Memory (Words) 44,032 87,552 Device PIC24FJ128DAXXX PIC24FJ256DAXXX Configuration Word Addresses 0x0157F8:0x0157FE 0x02ABF8:0x02ABFE FIGURE 4-2: msw Address 0x000001 0x000003 0x000005 0x000007 PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address) DS39969B-page 46 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 4.2 Note: Data Memory Space This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 45. "Data Memory with Extended Data Space" (DS39733). The information in this data sheet supersedes the information in the FRM. The PIC24F core has a 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 4-3. The 16-bit wide data addresses in the data memory space point to bytes within the Data Space (DS). This gives a DS address range of 64 Kbytes or 32K words. The lower 32 Kbytes (0x0000 to 0x7FFF) of DS is compatible with the PIC24F microcontrollers without EDS. The upper 32 Kbytes of data memory address space (0x8000 - 0xFFFF) are used as an EDS window. The EDS window is used to access all memory region implemented in EDS, as shown in Figure 4-4. The EDS includes any additional internal data memory not accessible by the lower 32-Kbyte data address space and any external memory through EPMP. For more details on accessing internal extended data memory, refer to the "PIC24F Family Reference Manual", Section 45. "Data Memory with Extended Data Space (EDS)" (DS39733). For more details on accessing external memory using EPMP, refer to the "PIC24F Family Reference Manual", Section 42. "Enhanced Parallel Master Port (EPMP)" (DS39730). In PIC24F microcontrollers with EDS, the program memory can also be read from EDS. This is called Program Space Visibility (PSV). Table 4-2 lists the total memory accessible by each of the devices in this family. The EDS is organized as pages, with a single page called an EDS page that equals the EDS window (32 Kbytes). A particular EDS page is selected through the Data Space Read register (DSRPAG) or Data Space Write register (DSWPAG). For PSV, only the DSRPAG register is used. The combination of the DSRPAG register value and the 16-bit wide data address forms a 24-bit Effective Address (EA). For more information on EDS, refer to Section 4.3.3 "Reading Data from Program Memory Using EDS". TABLE 4-2: Devices TOTAL MEMORY ACCESSIBLE BY THE DEVICE Internal RAM 96 Kbytes (30K + 66K(1)) 96 Kbytes (30K + 24 Kbytes 24 Kbytes 66K(1)) External RAM Access Using EPMP Yes (up to 16 MB) No Yes (up to 16 MB) No Program Memory Access Using EDS Yes Yes Yes Yes PIC24FJXXXDA210 PIC24FJXXXDA206 PIC24FJXXXDA110 PIC24FJXXXDA106 Note 1: The internal RAM above 30 Kbytes can be accessed through EDS window. 2010 Microchip Technology Inc. DS39969B-page 47 PIC24FJ256DA210 FAMILY 4.2.1 DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. FIGURE 4-3: MSB Address 0001h 07FFh 0801h 1FFFh 2001h DATA SPACE MEMORY MAP FOR PIC24FJ256DA210 FAMILY DEVICES(4) MSB SFR Space LSB LSB Address 0000h 07FEh 0800h 1FFEh 2000h SFR Space Near Data Space Lower 32 Kbytes Data Space 67FFh(1) 30 Kbytes Data RAM 67FEh(1) 7FFFh 8001h 7FFEh 8000h EDS Page 0x1 (32 KB) EDS Page 0x2 (32 KB) EDS Page 0x3 (2 KB) Internal Extended Data RAM(66 Kbytes)(2) Upper 32 Kbytes Data Space EDS Window EDS Page 0x4 EDS Page 0x1FF EDS Page 0x200 EDS Page 0x2FF EDS Page 0x300 EDS Page 0x3FF EPMP Memory Space(3) Program Space Visibility Area to Access Lower Word of Program Memory Program Space Visibility Area to Access Upper Word of Program Memory FFFFh FFFEh Note 1: 2: 3: 4: 24-Kbyte RAM variants (PIC24FJXXXDA1XX devices have implemented RAM only up to 0x67FF). Valid only for 96-Kbyte RAM variants (PIC24FJXXXDA2XX). Valid only for variants with the EPMP module (PIC24FJXXXDAX10). Data memory areas are not shown to scale. DS39969B-page 48 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC(R) MCUs and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word, which contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the LSB. The Most Significant Byte (MSB) is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 4.2.3 NEAR DATA SPACE The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field. 4.2.4 SPECIAL FUNCTION REGISTER (SFR) SPACE The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. A diagram of the SFR space, showing where the SFRs are actually implemented, is shown in Table 4-3. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete list of implemented SFRs, including their addresses, is shown in Tables 4-4 throughTable 4-34. TABLE 4-3: IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 Core Timers I2CTM -- -- EPMP UART ADC/CTMU -- -- RTC/Comp -- -- CRC System SPI/UART xx40 xx60 ICN Capture SPI/I2C -- -- -- -- NVM/PMD -- -- SPI -- UART -- USB -- PPS -- -- -- -- xx80 xxA0 xxC0 Compare I/O -- ANSEL -- -- -- xxE0 000h 100h 200h 300h 400h 500h 600h 700h Interrupts GFX Controller Legend: -- = No implemented SFRs in this block 2010 Microchip Technology Inc. DS39969B-page 49 DS39969B-page 50 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 4-4: File Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH DSRPAG DSWPAG(1) RCOUNT SR CORCON DISICNT TBLPAG Legend: Note 1: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052 0054 CPU CORE REGISTERS MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter Register High Byte Extended Data Space Read Page Address Register -- -- -- -- DC -- -- IPL2 -- Extended Data Space Write Page Address Register IPL1 -- IPL0 -- RA -- N IPL3 OV r Z -- C -- Repeat Loop Counter Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0001 0001 xxxx 0000 0004 xxxx 0000 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Value Register Program Counter Low Word Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Disable Interrupts Counter Register Table Memory Page Address Register -- = unimplemented, read as `0'; r = Reserved bit. Reset values are shown in hexadecimal. Reserved in PIC24FJXXXDA106 devices; do not use. 2010 Microchip Technology Inc. DS39969B-page 51 TABLE 4-5: File Name CNPD1 CNPD2 CNPD3 CNPD4 CNPD5 CNPD6 CNEN1 CNEN2 CNEN3 CNEN4 CNEN5 CNEN6 CNPU1 CNPU2 CNPU3 CNPU4 CNPU5 CNPU6 Addr 0056 0058 005C 0060 0062 0064 0066 0068 006A 006C 006E 0070 0074 0078 Bit 15 ICN REGISTER MAP Bit 14 CN14PDE CN30PDE CN62PDE -- CN14IE CN30IE CN46IE(1) CN62IE CN78IE(1) -- CN14PUE CN30PUE CN62PUE -- Bit 13 CN13PDE CN29PDE CN61PDE -- CN13IE CN29IE CN45IE(1) CN61IE CN77IE(1) -- CN13PUE CN29PUE CN61PUE -- Bit 12 CN12PDE CN28PDE CN60PDE -- CN12IE CN28IE CN44IE(1) CN60IE CN76IE(1) -- CN12PUE CN28PUE CN60PUE -- Bit 11 CN11PDE CN27PDE CN59PDE -- CN11IE CN27IE CN43IE(1) CN59IE CN75IE(1) -- CN11PUE CN27PUE CN59PUE -- Bit 10 CN10PDE CN26PDE CN58PDE -- CN10IE CN26IE CN42IE(1) CN58IE CN74IE(1) -- CN10PUE CN26PUE CN58PUE -- Bit 9 CN9PDE CN25PDE CN57PDE(1) -- CN9IE CN25IE CN41IE(1) CN57IE(1) CN73IE(1) -- CN9PUE CN25PUE CN57PUE(1) -- Bit 8 CN8PDE CN24PDE CN56PDE -- -- CN8IE CN24IE CN40IE(1) CN56IE -- -- CN8PUE CN24PUE CN56PUE -- -- Bit 7 CN7PDE CN23PDE CN55PDE CN71PDE -- CN7IE CN23IE CN39IE(1) CN55IE CN71IE -- CN7PUE CN23PUE CN55PUE CN71PUE -- Bit 6 CN6PDE CN22PDE CN54PDE CN70PDE(1) -- CN6IE CN22IE CN38IE(1) CN54IE CN70IE(1) -- CN6PUE CN22PUE CN54PUE CN70PUE(1) -- Bit 5 CN5PDE Bit 4 CN4PDE Bit 3 CN3PDE Bit 2 CN2PDE CN18PDE CN50PDE Bit 1 CN1PDE CN17PDE CN49PDE CN65PDE CN1IE CN17IE CN33IE(1) CN49IE CN65IE CN81IE(1) CN1PUE CN17PUE CN49PUE CN65PUE Bit 0 CN0PDE CN16PDE CN32PDE CN48PDE(1) CN64PDE CN0IE CN16IE CN32IE CN48IE(1) CN64IE CN80IE(1) CN0PUE CN16PUE CN32PUE CN48PUE(1) CN64PUE All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CN15PDE CN31PDE CN63PDE -- CN15IE CN31IE CN47IE(1) CN63IE CN79IE(1) -- CN15PUE CN31PUE CN63PUE -- CN21PDE(1) CN20PDE(1) CN19PDE(1) CN53PDE CN69PDE -- CN5IE CN21IE(1) CN37IE(1) CN53IE CN69IE -- CN5PUE CN52PDE CN68PDE CN84PDE CN4IE CN20IE(1) CN36IE(1) CN52IE CN68IE CN84IE CN4PUE CN51PDE CN83PDE CN3IE CN19IE(1) CN35IE(1) CN51IE CN67IE(1) CN83IE CN3PUE 005A CN47PDE(1) CN46PDE(1) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(1) CN39PDE(1) CN38PDE(1) CN37PDE(1) CN36PDE(1) CN35PDE(1) CN34PDE(1) CN33PDE(1) 005E CN79PDE(1) CN78PDE(1) CN77PDE(1) CN76PDE(1) CN75PDE(1) CN74PDE(1) CN73PDE(1) CN67PDE(1) CN66PDE(1) CN2IE CN18IE CN34IE(1) CN50IE CN66IE(1) CN82IE(1) CN2PUE CN18PUE CN50PUE CN82PDE(1) CN81PDE(1) CN80PDE(1) PIC24FJ256DA210 FAMILY CN21PUE(1) CN20PUE(1) CN19PUE(1) CN53PUE CN69PUE -- CN52PUE CN68PUE CN84PUE CN51PUE CN83PUE 0072 CN47PUE(1) CN46PUE(1) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(1) CN39PUE(1) CN38PUE(1) CN37PUE(1) CN36PUE(1) CN35PUE(1) CN34PUE(1) CN33PUE(1) 0076 CN79PUE(1) CN78PUE(1) CN77PUE(1) CN76PUE(1) CN75PUE(1) CN74PUE(1) CN73PUE(1) -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices; read as `0'. CN67PUE(1) CN66PUE(1) CN82PUE(1) CN81PUE(1) CN80PUE(1) Legend: Note 1: DS39969B-page 52 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 4-6: File Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IFS5 IFS6 IEC0 IEC1 IEC2 IEC3 IEC4 IEC5 IEC6 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 IPC15 Legend: Note 1: 2: Addr 0080 0082 0084 0086 0088 008A 008C 008E 0090 0094 0096 0098 009A 009C 009E 00A0 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00BE 00C2 INTERRUPT CONTROLLER REGISTER MAP Bit 15 NSTDIS ALTIVT -- U2TXIF -- -- -- -- -- -- U2TXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 14 -- DISI -- U2RXIF -- RTCIF -- -- -- -- U2RXIE -- RTCIE -- -- -- T1IP2 T2IP2 U1RXIP2 -- CNIP2 IC8IP2 T4IP2 U2TXIP2 -- IC5IP2 OC7IP2 -- -- -- -- Bit 13 -- -- AD1IF INT2IF PMPIF(1) -- CTMUIF IC9IF -- AD1IE INT2IE PMPIE(1) -- CTMUIE IC9IE -- T1IP1 T2IP1 U1RXIP1 -- CNIP1 IC8IP1 T4IP1 U2TXIP1 -- IC5IP1 OC7IP1 -- -- -- -- Bit 12 -- -- U1TXIF T5IF OC8IF -- -- OC9IF -- U1TXIE T5IE OC8IE -- -- OC9IE -- T1IP0 T2IP0 U1RXIP0 -- CNIP0 IC8IP0 T4IP0 U2TXIP0 -- IC5IP0 OC7IP0 -- -- -- -- Bit 11 -- -- U1RXIF T4IF OC7IF -- -- SPI3IF -- U1RXIE T4IE OC7IE -- -- SPI3IE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 10 -- -- SPI1IF OC4IF OC6IF -- -- SPF3IF -- SPI1IE OC4IE OC6IE -- -- SPF3IE -- OC1IP2 OC2IP2 SPI1IP2 -- CMIP2 IC7IP2 OC4IP2 U2RXIP2 -- IC4IP2 OC6IP2 -- MI2C2IP2 INT4IP2 RTCIP2 Bit 9 -- -- SPF1IF OC3IF OC5IF -- -- U4TXIF -- SPF1IE OC3IE OC5IE -- -- U4TXIE -- OC1IP1 OC2IP1 SPI1IP1 -- CMIP1 IC7IP1 OC4IP1 U2RXIP1 -- IC4IP1 OC6IP1 -- MI2C2IP1 INT4IP1 RTCIP1 Bit 8 -- -- T3IF -- IC6IF -- LVDIF U4RXIF -- T3IE -- IC6IE -- LVDIE U4RXIE -- OC1IP0 OC2IP0 SPI1IP0 -- CMIP0 IC7IP0 OC4IP0 U2RXIP0 -- IC4IP0 OC6IP0 -- MI2C2IP0 INT4IP0 RTCIP0 Bit 7 -- -- T2IF IC8IF IC5IF -- -- U4ERIF -- T2IE IC8IE IC5IE -- -- U4ERIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 6 -- -- OC2IF IC7IF IC4IF INT4IF -- USB1IF -- OC2IE IC7IE IC4IE INT4IE -- USB1IE -- IC1IP2 IC2IP2 SPF1IP2 AD1IP2 MI2C1IP2 -- OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2(1) SI2C2IP2 INT3IP2 -- Bit 5 -- -- IC2IF -- IC3IF INT3IF -- MI2C3IF -- IC2IE -- IC3IE INT3IE -- MI2C3IE -- IC1IP1 IC2IP1 SPF1IP1 AD1IP1 MI2C1IP1 -- OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1(1) SI2C2IP1 INT3IP1 -- Bit 4 MATHERR INT4EP -- INT1IF -- -- -- SI2C3IF GFX1IF -- INT1IE -- -- -- SI2C3IE GFX1IE IC1IP0 IC2IP0 SPF1IP0 AD1IP0 MI2C1IP0 -- OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0(1) SI2C2IP0 INT3IP0 -- Bit 3 ADDRERR INT3EP T1IF CNIF -- -- CRCIF U3TXIF -- T1IE CNIE -- -- CRCIE U3TXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 STKERR INT2EP OC1IF CMIF -- MI2C2IF U2ERIF U3RXIF -- OC1IE CMIE -- MI2C2IE U2ERIE U3RXIE -- INT0IP2 -- T3IP2 U1TXIP2 SI2C1IP2 INT1IP2 -- T5IP2 SPF2IP2 -- IC6IP2 OC8IP2 -- -- -- Bit 1 OSCFAIL INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1ERIF U3ERIF -- IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE U3ERIE -- INT0IP1 -- T3IP1 U1TXIP1 SI2C1IP1 INT1IP1 -- T5IP1 SPF2IP1 -- IC6IP1 OC8IP1 -- -- -- Bit 0 -- INT0EP INT0IF SI2C1IF SPF2IF -- -- -- -- INT0IE SI2C1IE SPF2IE -- -- -- -- INT0IP0 -- T3IP0 U1TXIP0 SI2C1IP0 INT1IP0 -- T5IP0 SPF2IP0 -- IC6IP0 OC8IP0 -- -- -- All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 4404 4440 4444 0044 4440 4444 0044(2) 0440 0440 0400 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices, read as `0'. The Reset value in 64-pin devices are `0004'. TABLE 4-6: File Name IPC16 IPC18 IPC19 IPC20 IPC21 IPC22 IPC23 IPC25 INTTREG Legend: Note 1: 2: Addr 00C4 00C8 00CA 00CC 00CE 00D0 00D2 00D6 00E0 INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) Bit 15 -- -- -- -- -- -- -- -- CPUIRQ Bit 14 CRCIP2 -- -- U3TXIP2 U4ERIP2 SPI3IP2 -- -- -- Bit 13 CRCIP1 -- -- U3TXIP1 U4ERIP1 SPI3IP1 -- -- VHOLD Bit 12 CRCIP0 -- -- U3TXIP0 U4ERIP0 SPI3IP0 -- -- -- Bit 11 -- -- -- -- -- -- -- -- ILR3 Bit 10 U2ERIP2 -- -- U3RXIP2 USB1IP2 SPF3IP2 -- -- ILR2 Bit 9 U2ERIP1 -- -- U3RXIP1 USB1IP1 SPF3IP1 -- -- ILR1 Bit 8 U2ERIP0 -- -- U3RXIP0 USB1IP0 SPF3IP0 -- -- ILR0 Bit 7 -- -- -- -- -- -- -- -- -- Bit 6 U1ERIP2 -- CTMUIP2 U3ERIP2 MI2C3IP2 U4TXIP2 IC9IP2 -- VECNUM6 Bit 5 U1ERIP1 -- CTMUIP1 U3ERIP1 MI2C3IP1 U4TXIP1 IC9IP1 -- VECNUM5 Bit 4 U1ERIP0 -- CTMUIP0 U3ERIP0 MI2C3IP0 U4TXIP0 IC9IP0 -- VECNUM4 Bit 3 -- -- -- -- -- -- -- -- VECNUM3 Bit 2 -- LVDIP2 -- -- SI2C3IP2 U4RXIP2 OC9IP2 GFX1IP2 Bit 1 -- LVDIP1 -- -- SI2C3IP1 U4RXIP1 OC9IP1 GFX1IP1 Bit 0 -- LVDIP0 -- -- SI2C3IP0 U4RXIP0 OC9IP0 GFX1IP0 All Resets 4440 0004 0040 4440 4444 4444 0044 0004 0000 2010 Microchip Technology Inc. DS39969B-page 53 VECNUM2 VECNUM1 VECNUM0 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices, read as `0'. The Reset value in 64-pin devices are `0004'. TABLE 4-7: File Name TMR1 PR1 T1CON TMR2 TMR3HLD TMR3 PR2 PR3 T2CON T3CON TMR4 TMR5HLD TMR5 PR4 PR5 T4CON T5CON Legend: Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120 TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF TGATE TCKPS1 TCKPS0 -- TSYNC TCS -- 0000 0000 0000 0000 FFFF FFFF TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 -- -- -- TCS TCS -- -- 0000 0000 0000 0000 0000 FFFF FFFF TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T45 -- -- -- TCS TCS -- -- 0000 0000 PIC24FJ256DA210 FAMILY Timer1 Register Timer1 Period Register TON -- TSIDL -- -- -- -- -- -- Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- -- -- -- Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Timer4 Period Register Timer5 Period Register TON TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- -- -- -- -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS39969B-page 54 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 4-8: File Name IC1CON1 IC1CON2 IC1BUF IC1TMR IC2CON1 IC2CON2 IC2BUF IC2TMR IC3CON1 IC3CON2 IC3BUF IC3TMR IC4CON1 IC4CON2 IC4BUF IC4TMR IC5CON1 IC5CON2 IC5BUF IC5TMR IC6CON1 IC6CON2 IC6BUF IC6TMR IC7CON1 IC7CON2 IC7BUF IC7TMR IC8CON1 IC8CON2 IC8BUF IC8TMR IC9CON1 IC9CON2 IC9BUF IC9TMR Legend: Addr 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152 0154 0156 0158 015A 015C 015E 0160 0162 0164 0166 0168 016A 016C 016E 0170 0172 0174 0176 0178 017A 017C 017E 0180 0182 0184 0186 INPUT CAPTURE REGISTER MAP Bit 15 -- -- Bit 14 -- -- Bit 13 ICSIDL -- Bit 12 ICTSEL2 -- Bit 11 ICTSEL1 -- Bit 10 ICTSEL0 -- Bit 9 -- -- Bit 8 -- IC32 Bit 7 -- ICTRIG Bit 6 ICI1 TRIGSTAT Bit 5 ICI0 -- Bit 4 ICOV SYNCSEL4 Bit 3 ICBNE SYNCSEL3 Bit 2 ICM2 SYNCSEL2 Bit 1 ICM1 SYNCSEL1 Bit 0 ICM0 SYNCSEL0 All Resets 0000 000D 0000 xxxx ICI0 -- ICOV SYNCSEL4 ICBNE SYNCSEL3 ICM2 SYNCSEL2 ICM1 SYNCSEL1 ICM0 SYNCSEL0 0000 000D 0000 xxxx ICI0 -- ICOV SYNCSEL4 ICBNE SYNCSEL3 ICM2 SYNCSEL2 ICM1 SYNCSEL1 ICM0 SYNCSEL0 0000 000D 0000 xxxx ICI0 -- ICOV SYNCSEL4 ICBNE SYNCSEL3 ICM2 SYNCSEL2 ICM1 SYNCSEL1 ICM0 SYNCSEL0 0000 000D 0000 xxxx ICI0 -- ICOV SYNCSEL4 ICBNE SYNCSEL3 ICM2 SYNCSEL2 ICM1 SYNCSEL1 ICM0 SYNCSEL0 0000 000D 0000 xxxx ICI0 -- ICOV SYNCSEL4 ICBNE SYNCSEL3 ICM2 SYNCSEL2 ICM1 SYNCSEL1 ICM0 SYNCSEL0 0000 000D 0000 xxxx ICI0 -- ICOV SYNCSEL4 ICBNE SYNCSEL3 ICM2 SYNCSEL2 ICM1 SYNCSEL1 ICM0 SYNCSEL0 0000 000D 0000 xxxx ICI0 -- ICOV SYNCSEL4 ICBNE SYNCSEL3 ICM2 SYNCSEL2 ICM1 SYNCSEL1 ICM0 SYNCSEL0 0000 000D 0000 xxxx ICI0 -- ICOV SYNCSEL4 ICBNE SYNCSEL3 ICM2 SYNCSEL2 ICM1 SYNCSEL1 ICM0 SYNCSEL0 0000 000D 0000 xxxx Input Capture 1 Buffer Register Input Capture 1 Timer Value Register -- -- -- -- ICSIDL -- ICTSEL2 -- ICTSEL1 -- ICTSEL0 -- -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 2 Buffer Register Input Capture 2 Timer Value Register -- -- -- -- ICSIDL -- ICTSEL2 -- ICTSEL1 -- ICTSEL0 -- -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 3 Buffer Register Input Capture 3 Timer Value Register -- -- -- -- ICSIDL -- ICTSEL2 -- ICTSEL1 -- ICTSEL0 -- -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 4 Buffer Register Input Capture 4 Timer Value Register -- -- -- -- ICSIDL -- ICTSEL2 -- ICTSEL1 -- ICTSEL0 -- -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 5 Buffer Register Input Capture 5 Timer Value Register -- -- -- -- ICSIDL -- ICTSEL2 -- ICTSEL1 -- ICTSEL0 -- -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 6 Buffer Register Input Capture 6 Timer Value Register -- -- -- -- ICSIDL -- ICTSEL2 -- ICTSEL1 -- ICTSEL0 -- -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 7 Buffer Register Input Capture 7 Timer Value Register -- -- -- -- ICSIDL -- ICTSEL2 -- ICTSEL1 -- ICTSEL0 -- -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 8 Buffer Register Input Capture 8 Timer Value Register -- -- -- -- ICSIDL -- ICTSEL2 -- ICTSEL1 -- ICTSEL0 -- -- -- -- IC32 -- ICTRIG ICI1 TRIGSTAT Input Capture 9 Buffer Register Input Capture 9 Timer Value Register -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 2010 Microchip Technology Inc. DS39969B-page 55 TABLE 4-9: File Name Addr OC1CON1 OC1CON2 OC1RS OC1R OC1TMR OC2CON1 OC2CON2 OC2RS OC2R OC2TMR OC3CON1 OC3CON2 OC3RS OC3R OC3TMR OC4CON1 OC4CON2 OC4RS OC4R OC4TMR OC5CON1 OC5CON2 OC5RS OC5R OC5TMR OC6CON1 OC6CON2 OC6RS OC6R OC6TMR OC7CON1 OC7CON2 OC7RS OC7R OC7TMR Legend: 0190 0192 0194 0196 0198 019A 019C 019E 01A0 01A2 01A4 01A6 01A8 01AA 01AC 01AE 01B0 01B2 01B4 01B6 01B8 01BA 01BC 01BE 01C0 01C2 01C4 01C6 01C8 01CA 01CC 01CE 01D0 01D2 01D4 OUTPUT COMPARE REGISTER MAP Bit 15 -- FLTMD Bit 14 -- FLTOUT Bit 13 OCSIDL FLTTRIEN Bit 12 OCTSEL2 OCINV Bit 11 OCTSEL1 -- Bit 10 OCTSEL0 DCB1 Bit 9 ENFLT2 DCB0 Bit 8 ENFLT1 OC32 Bit 7 ENFLT0 OCTRIG Bit 6 OCFLT2 TRIGSTAT Bit 5 OCFLT1 OCTRIS Bit 4 OCFLT0 SYNCSEL4 Bit 3 TRIGMODE SYNCSEL3 Bit 2 OCM2 SYNCSEL2 Bit 1 OCM1 SYNCSEL1 Bit 0 OCM0 SYNCSEL0 All Resets 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 SYNCSEL4 TRIGMODE SYNCSEL3 OCM2 SYNCSEL2 OCM1 SYNCSEL1 OCM0 SYNCSEL0 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 SYNCSEL4 TRIGMODE SYNCSEL3 OCM2 SYNCSEL2 OCM1 SYNCSEL1 OCM0 SYNCSEL0 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 SYNCSEL4 TRIGMODE SYNCSEL3 OCM2 SYNCSEL2 OCM1 SYNCSEL1 OCM0 SYNCSEL0 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 SYNCSEL4 TRIGMODE SYNCSEL3 OCM2 SYNCSEL2 OCM1 SYNCSEL1 OCM0 SYNCSEL0 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 SYNCSEL4 TRIGMODE SYNCSEL3 OCM2 SYNCSEL2 OCM1 SYNCSEL1 OCM0 SYNCSEL0 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 SYNCSEL4 TRIGMODE SYNCSEL3 OCM2 SYNCSEL2 OCM1 SYNCSEL1 OCM0 SYNCSEL0 0000 000C 0000 0000 xxxx Output Compare 1 Secondary Register Output Compare 1 Register Output Compare 1 Timer Value Register -- FLTMD -- FLTOUT OCSIDL FLTTRIEN OCTSEL2 OCINV OCTSEL1 -- OCTSEL0 DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT Output Compare 2 Secondary Register Output Compare 2 Register Output Compare 2 Timer Value Register -- FLTMD -- FLTOUT OCSIDL FLTTRIEN OCTSEL2 OCINV OCTSEL1 -- OCTSEL0 DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT Output Compare 3 Secondary Register Output Compare 3 Register Output Compare 3 Timer Value Register -- FLTMD -- FLTOUT OCSIDL FLTTRIEN OCTSEL2 OCINV OCTSEL1 -- OCTSEL0 DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT PIC24FJ256DA210 FAMILY Output Compare 4 Secondary Register Output Compare 4 Register Output Compare 4 Timer Value Register -- FLTMD -- FLTOUT OCSIDL FLTTRIEN OCTSEL2 OCINV OCTSEL1 -- OCTSEL0 DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT1 TRIGSTAT Output Compare 5 Secondary Register Output Compare 5 Register Output Compare 5 Timer Value Register -- FLTMD -- FLTOUT OCSIDL FLTTRIEN OCTSEL2 OCINV OCTSEL1 -- OCTSEL0 DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT Output Compare 6 Secondary Register Output Compare 6 Register Output Compare 6 Timer Value Register -- FLTMD -- FLTOUT OCSIDL FLTTRIEN OCTSEL2 OCINV OCTSEL1 -- OCTSEL0 DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT Output Compare 7 Secondary Register Output Compare 7 Register Output Compare 7 Timer Value Register -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-9: File Name Addr OC8CON1 OC8CON2 OC8RS OC8R OC8TMR OC9CON1 OC9CON2 OC9RS OC9R OC9TMR Legend: 01D6 01D8 01DA 01DC 01DE 01E0 01E2 01E4 01E6 01E8 OUTPUT COMPARE REGISTER MAP (CONTINUED) Bit 15 -- FLTMD Bit 14 -- FLTOUT Bit 13 OCSIDL FLTTRIEN Bit 12 OCTSEL2 OCINV Bit 11 OCTSEL1 -- Bit 10 OCTSEL0 DCB1 Bit 9 ENFLT2 DCB0 Bit 8 ENFLT1 OC32 Bit 7 ENFLT0 OCTRIG Bit 6 OCFLT2 TRIGSTAT Bit 5 OCFLT1 OCTRIS Bit 4 OCFLT0 SYNCSEL4 Bit 3 TRIGMODE SYNCSEL3 Bit 2 OCM2 SYNCSEL2 Bit 1 OCM1 SYNCSEL1 Bit 0 OCM0 SYNCSEL0 All Resets 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 SYNCSEL4 TRIGMODE SYNCSEL3 OCM2 SYNCSEL2 OCM1 SYNCSEL1 OCM0 SYNCSEL0 0000 000C 0000 0000 xxxx DS39969B-page 56 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Output Compare 8 Secondary Register Output Compare 8 Register Output Compare 8 Timer Value Register -- FLTMD -- FLTOUT OCSIDL FLTTRIEN OCTSEL2 OCINV OCTSEL1 -- OCTSEL0 DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT Output Compare 9 Secondary Register Output Compare 9 Register Output Compare 9 Timer Value Register -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-10: File Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK I2C3RCV I2C3TRN I2C3BRG I2C3CON I2C3STAT I2C3ADD I2C3MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C 0210 0212 0214 0216 0218 021A 021C 0270 0272 0274 0276 0278 027A 027C I2CTM REGISTER MAP Bit 15 -- -- -- I2CEN ACKSTAT -- -- -- -- -- I2CEN ACKSTAT -- -- -- -- -- I2CEN ACKSTAT -- -- Bit 14 -- -- -- -- TRSTAT -- -- -- -- -- -- TRSTAT -- -- -- -- -- -- TRSTAT -- -- Bit 13 -- -- -- I2CSIDL -- -- -- -- -- -- I2CSIDL -- -- -- -- -- -- I2CSIDL -- -- -- Bit 12 -- -- -- SCLREL -- -- -- -- -- -- SCLREL -- -- -- -- -- -- SCLREL -- -- -- Bit 11 -- -- -- IPMIEN -- -- -- -- -- -- IPMIEN -- -- -- -- -- -- IPMIEN -- -- -- Bit 10 -- -- -- A10M BCL -- -- -- -- -- A10M BCL -- -- -- -- -- A10M BCL -- -- -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV -- -- ACKDT D/A -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV -- -- ACKDT D/A Bit 9 -- -- -- DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 -- -- ACKDT D/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R/W RSEN RBF SEN TBF 1000 0000 0000 0000 0000 00FF 0000 PEN R/W RSEN RBF SEN TBF 1000 0000 0000 0000 0000 00FF 0000 PEN R/W RSEN RBF SEN TBF 1000 0000 0000 0000 I2C1 Receive Register I2C1 Transmit Register I2C1 Baud Rate Generator Register ACKEN P RCEN S I2C1 Address Register I2C1 Address Mask Register I2C2 Receive Register I2C2 Transmit Register I2C2 Baud Rate Generator Register ACKEN P RCEN S I2C2 Address Register I2C2 Address Mask Register I2C3 Receive Register I2C3 Transmit Register I2C3 Baud Rate Generator Register ACKEN P RCEN S I2C3 Address Register I2C3 Address Mask Register -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-11: File Name U1MODE U1STA U1TXREG U1RXREG U1BRG U2MODE U2STA U2TXREG U2RXREG U2BRG U3MODE U3STA U3TXREG U3RXREG U3BRG U4MODE U4STA U4TXREG U4RXREG U4BRG Legend: Addr 0220 0222 0224 0226 0228 0230 0232 0234 0236 0238 0250 0252 0254 0256 0258 02B0 02B2 02B4 02B6 02B8 UART REGISTER MAPS Bit 15 UARTEN UTXISEL1 -- -- UARTEN UTXISEL1 -- -- UARTEN UTXISEL1 -- -- UARTEN UTXISEL1 -- -- Bit 14 -- UTXINV -- -- -- UTXINV -- -- -- UTXINV -- -- -- UTXINV -- -- Bit 13 USIDL UTXISEL0 -- -- USIDL UTXISEL0 -- -- USIDL UTXISEL0 -- -- USIDL UTXISEL0 -- -- Bit 12 IREN -- -- -- IREN -- -- -- IREN -- -- -- IREN -- -- -- Bit 11 RTSMD UTXBRK -- -- RTSMD UTXBRK -- -- RTSMD UTXBRK -- -- RTSMD UTXBRK -- -- Bit 10 -- UTXEN -- -- -- UTXEN -- -- -- UTXEN -- -- -- UTXEN -- -- Bit 9 UEN1 UTXBF -- -- UART1 Baud Rate Generator Prescaler Register UEN1 UTXBF -- -- UART2 Baud Rate Generator Prescaler Register UEN1 UTXBF -- -- UART3 Baud Rate Generator Prescaler Register UEN1 UTXBF -- -- UART4 Baud Rate Generator Prescaler Register UEN0 TRMT WAKE URXISEL1 LPBACK URXISEL0 ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA UEN0 TRMT WAKE URXISEL1 LPBACK URXISEL0 ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA UEN0 TRMT WAKE URXISEL1 LPBACK URXISEL0 ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA Bit 8 UEN0 TRMT Bit 7 WAKE URXISEL1 Bit 6 LPBACK URXISEL0 Bit 5 ABAUD ADDEN Bit 4 RXINV RIDLE Bit 3 BRGH PERR Bit 2 PDSEL1 FERR Bit 1 PDSEL0 OERR Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx 2010 Microchip Technology Inc. DS39969B-page 57 UART1 Transmit Register UART1 Receive Register UART2 Transmit Register UART2 Receive Register UART3 Transmit Register UART3 Receive Register PIC24FJ256DA210 FAMILY 0000 0000 0000 0110 xxxx 0000 0000 UART4 Transmit Register UART4 Receive Register -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS39969B-page 58 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 4-12: File Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF SPI3STAT SPI3CON1 SPI3CON2 SPI3BUF Legend: Addr 0240 0242 0244 0248 0260 0262 0264 0268 0280 0282 0284 0288 SPI REGISTER MAPS Bit 15 SPIEN -- FRMEN SPIEN -- FRMEN SPIEN -- FRMEN Bit 14 -- -- SPIFSD -- -- SPIFSD -- -- SPIFSD Bit 13 SPISIDL -- SPIFPOL SPISIDL -- SPIFPOL SPISIDL -- SPIFPOL Bit 12 -- DISSCK -- -- DISSCK -- -- DISSCK -- Bit 11 -- DISSDO -- -- DISSDO -- -- DISSDO -- Bit 10 SPIBEC2 MODE16 -- SPIBEC2 MODE16 -- SPIBEC2 MODE16 -- Bit 9 SPIBEC1 SMP -- SPIBEC1 SMP -- SPIBEC1 SMP -- Bit 8 SPIBEC0 CKE -- SPIBEC0 CKE -- SPIBEC0 CKE -- Bit 7 SRMPT SSEN -- SRMPT SSEN -- SRMPT SSEN -- Bit 6 SPIROV CKP -- SPIROV CKP -- SPIROV CKP -- Bit 5 SRXMPT MSTEN -- SRXMPT MSTEN -- SRXMPT MSTEN -- Bit 4 SISEL2 SPRE2 -- SISEL2 SPRE2 -- SISEL2 SPRE2 -- Bit 3 SISEL1 SPRE1 -- SISEL1 SPRE1 -- SISEL1 SPRE1 -- Bit 2 SISEL0 SPRE0 -- SISEL0 SPRE0 -- SISEL0 SPRE0 -- Bit 1 SPITBF PPRE1 SPIFE SPITBF PPRE1 SPIFE SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN SPIRBF PPRE0 SPIBEN SPIRBF PPRE0 SPIBEN All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SPI1 Transmit and Receive Buffer SPI2 Transmit and Receive Buffer SPI3 Transmit and Receive Buffer -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-13: File Name TRISA PORTA LATA ODCA Legend: Note 1: Addr 02C0 02C2 02C4 02C6 PORTA REGISTER MAP(1) Bit 15 TRISA15 RA15 LATA15 ODA15 Bit 14 TRISA14 RA14 LATA14 ODA14 Bit 13 -- -- -- -- Bit 12 -- -- -- -- Bit 11 -- -- -- -- Bit 10 TRISA10 RA10 LATA10 ODA10 Bit 9 TRISA9 RA9 LATA9 ODA9 Bit 8 -- -- -- -- Bit 7 TRISA7 RA7 LATA7 ODA7 Bit 6 TRISA6 RA6 LATA6 ODA6 Bit 5 TRISA5 RA5 LATA5 ODA5 Bit 4 TRISA4 RA4 LATA4 ODA4 Bit 3 TRISA3 RA3 LATA3 ODA3 Bit2 TRISA2 RA2 LATA2 ODA2 Bit 1 TRISA1 RA1 LATA1 ODA1 Bit 0 TRISA0 RA0 LATA0 ODA0 All Resets C6FF xxxx xxxx 0000 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. PORTA and all associated bits are unimplemented on 64-pin devices and read as `0'. Bits are available on 100-pin devices only, unless otherwise noted. TABLE 4-14: File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE PORTB REGISTER MAP Bit 15 TRISB15 RB15 LATB15 ODB15 Bit 14 TRISB14 RB14 LATB14 ODB14 Bit 13 TRISB13 RB13 LATB13 ODB13 Bit 12 TRISB12 RB12 LATB12 ODB12 Bit 11 TRISB11 RB11 LATB11 ODB11 Bit 10 TRISB10 RB10 LATB10 ODB10 Bit 9 TRISB9 RB9 LATB9 ODB9 Bit 8 TRISB8 RB8 LATB8 ODB8 Bit 7 TRISB7 RB7 LATB7 ODB7 Bit 6 TRISB6 RB6 LATB6 ODB6 Bit 5 TRISB5 RB5 LATB5 ODB5 Bit 4 TRISB4 RB4 LATB4 ODB4 Bit 3 TRISB3 RB3 LATB3 ODB3 Bit 2 TRISB2 RB2 LATB2 ODB2 Bit 1 TRISB1 RB1 LATB1 ODB1 Bit 0 TRISB0 RB0 LATB0 ODB0 All Resets FFFF xxxx xxxx 0000 Reset values are shown in hexadecimal. TABLE 4-15: File Name TRISC PORTC LATC ODCC Legend: Note 1: 2: 3: Addr 02D0 02D2 02D4 02D6 PORTC REGISTER MAP Bit 15 TRISC15 RC15(2,3) LATC15 ODC15 Bit 14 TRISC14 RC14 LATC14 ODC14 Bit 13 TRISC13 RC13 LATC13 ODC13 Bit 12 TRISC12 RC12(2) LATC12 ODC12 Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 -- -- -- -- Bit 8 -- -- -- -- Bit 7 -- -- -- -- Bit 6 -- -- -- -- Bit 5 -- -- -- -- Bit 4(1) TRISC4 RC4 LATC4 ODC4 Bit 3(1) TRISC3 RC3 LATC3 ODC3 Bit 2(1) TRISC2 RC2 LATC2 ODC2 Bit 1(1) TRISC1 RC1 LATC1 ODC1 Bit 0 -- -- -- -- All Resets F01E xxxx xxxx 0000 2010 Microchip Technology Inc. DS39969B-page 59 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin devices; read as `0'. RC12 and RC15 are only available when the primary oscillator is disabled or when EC mode is selected (POSCMD<1:0> Configuration bits = 11 or 00); otherwise read as `0'. RC15 is only available when the POSCMD<1:0> Configuration bits = 11 or 00 and the OSCIOFN Configuration bit = 1. TABLE 4-16: File Name TRISD PORTD LATD ODCD Legend: Note 1: Addr 02D8 02DA 02DC 02DE PORTD REGISTER MAP Bit 15(1) TRISD15 RD15 LATD15 ODD15 Bit 14(1) TRISD14 RD14 LATD14 ODD14 Bit 13(1) TRISD13 RD13 LATD13 ODD13 Bit 12(1) TRISD12 RD12 LATD12 ODD12 Bit 11 TRISD11 RD11 LATD11 ODD11 Bit 10 TRISD10 RD10 LATD10 ODD10 Bit 9 TRISD9 RD9 LATD9 ODD9 Bit 8 TRISD8 RD8 LATD8 ODD8 Bit 7 TRISD7 RD7 LATD7 ODD7 Bit 6 TRISD6 RD6 LATD6 ODD6 Bit 5 TRISD5 RD5 LATD5 ODD5 Bit 4 TRISD4 RD4 LATD4 ODD4 Bit 3 TRISD3 RD3 LATD3 ODD3 Bit 2 TRISD2 RD2 LATD2 ODD2 Bit 1 TRISD1 RD1 LATD1 ODD1 Bit 0 TRISD0 RD0 LATD0 ODD0 All Resets FFFF PIC24FJ256DA210 FAMILY xxxx xxxx 0000 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin devices; read as `0'. TABLE 4-17: File Name TRISE PORTE LATE ODCE Legend: Note 1: Addr 02E0 02E2 02E4 02E6 PORTE REGISTER MAP Bit 15 -- -- -- -- Bit 14 -- -- -- -- Bit 13 -- -- -- -- Bit 12 -- -- -- -- Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9(1) TRISE9 RE9 LATE9 ODE9 Bit 8(1) TRISE8 RE8 LATE8 ODE8 Bit 7 TRISE7 RE7 LATE7 ODE7 Bit 6 TRISE6 RE6 LATE6 ODE6 Bit 5 TRISE5 RE5 LATE5 ODE5 Bit 4 TRISE4 RE4 LATE4 ODE4 Bit 3 TRISE3 RE3 LATE3 ODE3 Bit 2 TRISE2 RE2 LATE2 ODE2 Bit 1 TRISE1 RE1 LATE1 ODE1 Bit 0 TRISE0 RE0 LATE0 ODE0 All Resets 03FF xxxx xxxx 0000 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin devices; read as `0'. DS39969B-page 60 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 4-18: File Name TRISF PORTF LATF ODCF Legend: Note 1: Addr 02E8 02EA 02EC 02EE PORTF REGISTER MAP Bit 15 -- -- -- -- Bit 14 -- -- -- -- Bit 13(1) TRISF13 RF13 LATF13 ODF13 Bit 12(1) TRISF12 RF12 LATF12 ODF12 Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 -- -- -- -- Bit 8(1) TRISF8 RF8 LATF8 ODF8 Bit 7 TRISF7 RF7 LATF7 ODF7 Bit 6 -- -- -- -- Bit 5 TRISF5 RF5 LATF5 ODF5 Bit 4 TRISF4 RF4 LATF4 ODF4 Bit 3 TRISF3 RF3 LATF3 ODF3 Bit 2(1) TRISF2 RF2 LATF2 ODF2 Bit 1 TRISF1 RF1 LATF1 ODF1 Bit 0 TRISF0 RF0 LATF0 ODF0 All Resets 31BF xxxx xxxx 0000 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin devices; read as `0'. TABLE 4-19: File Name TRISG PORTG LATG ODCG Legend: Note 1: Addr 02F0 02F2 02F4 02F6 PORTG REGISTER MAP Bit 15(1) TRISG15 RG15 LATG15 ODG15 Bit 14(1) TRISG14 RG14 LATG14 ODG14 Bit 13(1) TRISG13 RG13 LATG13 ODG13 Bit 12(1) TRISG12 RG12 LATG12 ODG12 Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 TRISG9 RG9 LATG9 ODG9 Bit 8 TRISG8 RG8 LATG8 ODG8 Bit 7 TRISG7 RG7 LATG7 ODG7 Bit 6 TRISG6 RG6 LATG6 ODG6 Bit 5 -- -- -- -- Bit 4 -- -- -- -- Bit 3 TRISG3 RG3 LATG3 ODG3 Bit 2 TRISG2 RG2 LATG2 ODG2 Bit 1(1) TRISG1 RG1 LATG1 ODG1 Bit 0(1) TRISG0 RG0 LATG0 ODG0 All Resets F3CF xxxx xxxx 0000 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin devices; read as `0'. TABLE 4-20: File Name PADCFG1 Legend: Note 1: Addr 02FC PAD CONFIGURATION REGISTER MAP Bit 15 -- Bit 14 -- Bit 13 -- Bit 12 -- Bit 11 -- Bit 10 -- Bit 9 -- Bit 8 -- Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 RTSECSEL Bit 0 PMPTTL(1) All Resets 0000 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bits are unimplemented in 64-pin devices; read as `0'. 2010 Microchip Technology Inc. DS39969B-page 61 TABLE 4-21: File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF ADC1BUF10 ADC1BUF11 ADC1BUF12 ADC1BUF13 ADC1BUF14 ADC1BUF15 ADC1BUF16 ADC1BUF17 ADC1BUF18 ADC1BUF19 ADC1BUF1A ADC1BUF1B ADC1BUF1C ADC1BUF1D ADC1BUF1E ADC1BUF1F Legend: Note 1: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0340 0342 0344 0346 0348 034A 034C 034E 0350 0352 0354 0356 0358 035A 035C 035E ADC REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADC Data Buffer 16 ADC Data Buffer 17 ADC Data Buffer 18 ADC Data Buffer 19 ADC Data Buffer 20 ADC Data Buffer21 ADC Data Buffer 22 ADC Data Buffer 23 ADC Data Buffer 24 ADC Data Buffer 25 ADC Data Buffer 26 ADC Data Buffer 27 ADC Data Buffer 28 ADC Data Buffer 29 ADC Data Buffer 30 ADC Data Buffer 31 PIC24FJ256DA210 FAMILY -- = unimplemented, read as `0', r = reserved, maintain as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices, read as `0' TABLE 4-21: File Name AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1CSSH AD1CSSL Legend: Note 1: Addr 0320 0322 0324 0328 032E 0330 ADC REGISTER MAP (CONTINUED) Bit 15 ADON VCFG2 ADRC CH0NB -- CSSL15 Bit 14 -- VCFG1 r -- -- CSSL14 Bit 13 ADSIDL VCFG0 r -- -- CSSL13 Bit 12 -- r SAMC4 CH0SB4 -- CSSL12 Bit 11 -- -- SAMC3 CH0SB3 CSSL27 CSSL11 Bit 10 -- CSCNA SAMC2 CH0SB2 CSSL26 CSSL10 Bit 9 FORM1 -- SAMC1 CH0SB1 CSSL25 CSSL9 Bit 8 FORM0 -- SAMC0 CH0SB0 CSSL24 CSSL8 Bit 7 SSRC2 BUFS ADCS7 CH0NA CSSL7 Bit 6 SSRC1 SMPI4 ADCS6 -- CSSL6 Bit 5 SSRC0 SMPI3 ADCS5 -- CSSL5 Bit 4 -- SMPI2 ADCS4 CH0SA4 CSSL4 Bit 3 -- SMPI1 ADCS3 CH0SA3 CSSL3 Bit 2 ASAM SMPI0 ADCS2 CH0SA2 CSSL2 Bit 1 SAMP BUFM ADCS1 CH0SA1 CSSL1 Bit 0 DONE ALTS ADCS0 CH0SA0 CSSL0 All Resets 0000 0000 0000 0000 0000 0000 DS39969B-page 62 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY CSSL23(1) CSSL22(1) CSSL21(1) CSSL20(1) CSSL19(1) CSSL18(1) CSSL17(1) CSSL16(1) -- = unimplemented, read as `0', r = reserved, maintain as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices, read as `0' TABLE 4-22: File Name CTMUCON Legend: Addr 033C CTMU REGISTER MAP Bit 15 CTMUEN ITRIM5 Bit 14 -- ITRIM4 Bit 13 CTMUSIDL ITRIM3 Bit 12 TGEN ITRIM2 Bit 11 EDGEN ITRIM1 Bit 10 EDGSEQEN ITRIM0 Bit 9 IDISSEN IRNG1 Bit 8 CTTRIG IRNG0 Bit 7 EDG2POL -- Bit 6 EDG2SEL1 -- Bit 5 EDG2SEL0 -- Bit 4 EDG1POL -- Bit 3 EDG1SEL1 -- Bit 2 EDG1SEL0 -- Bit 1 EDG2STAT -- Bit 0 EDG1STAT -- All Resets 0000 0000 CTMUICON 033E -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-23: File Name U1OTGIR(2) U1OTGIE(2) U1OTGSTAT2) U1OTGCON(2) U1PWRC U1IR U1IE U1EIR U1EIE U1STAT U1CON U1ADDR U1BDTP1 U1FRML U1FRMH U1TOK(2) U1SOF(2) U1CNFG1 U1CNFG2 U1EP0 U1EP1 U1EP2 U1EP3 U1EP4 U1EP5 U1EP6 Addr 0480 0482 0484 0486 0488 048A(1) 048C(1) 048E(1) 0490(1) 0492 0494(1) 0496 0498 049A 049C 049E 04A0 04A6 04A8 04AA 04AC 04AE 04B0 04B2 04B4 04B6 04B8 04BA 04BC USB OTG REGISTER MAP Bit 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UTEYE -- LSPD(1) -- -- -- -- -- -- -- -- -- UOEMON -- RETRYDIS(1) -- -- -- -- -- -- -- -- -- -- UVCMPSEL -- -- -- -- -- -- -- -- -- -- -- PID3 -- PID2 -- PID1 Bit 7 IDIF IDIE ID DPPULUP UACTPND STALLIF STALLIF STALLIE STALLIE BTSEF BTSEF BTSEE BTSEE ENDPT3 -- JSTATE(1) LSPDEN(1) Bit 6 T1MSECIF T1MSECIE -- DMPULUP -- -- ATTACHIF(1) -- ATTACHIE(1) -- -- -- -- ENDPT2 SE0 SE0 Bit 5 LSTATEIF LSTATEIE LSTATE -- RESUMEIF RESUMEIF RESUMEIE RESUMEIE DMAEF DMAEF DMAEE DMAEE ENDPT1 PKTDIS TOKBUSY Bit 4 ACTVIF ACTVIE -- USLPGRD IDLEIF IDLEIF IDLEIE IDLEIE BTOEF BTOEF BTOEE BTOEE ENDPT0 -- USBRST Bit 3 SESVDIF SESVDIE SESVD VBUSON -- TRNIF TRNIF TRNIE TRNIE DFN8EF DFN8EF DFN8EE DFN8EE DIR HOSTEN HOSTEN Bit 2 SESENDIF SESENDIE SESEND OTGEN -- SOFIF SOFIF SOFIE SOFIE CRC16EF CRC16EF CRC16EE CRC16EE PPBI RESUME RESUME Bit 1 -- -- -- VBUSCHG USUSPND UERRIF UERRIF UERRIE UERRIE CRC5EF EOFEF(1) CRC5EE EOFEE(1) -- PPBRST PPBRST Bit 0 VBUSVDIF VBUSVDIE VBUSVD VBUSDIS USBPWR URSTIF DETACHIF(1) URSTIE DETACHIE(1) PIDEF PIDEF PIDEE PIDEE -- USBEN SOFEN(1) -- Frame Count Register High Byte EP2 -- UVBUSDIS EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EP1 PPB1 UVCMPDIS EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EP0 PPB0 UTRDIS EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 2010 Microchip Technology Inc. DS39969B-page 63 DPPULDWN DMPULDWN PIC24FJ256DA210 FAMILY USB Device Address (DEVADDR) Register Buffer Descriptor Table Base Address Register Frame Count Register Low Byte -- PID0 USBSIDL PUVBUS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS -- EP3 -- EXTI2CEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN Start-Of-Frame Count Register U1EP7 U1EP8 U1EP9 Legend: Note 1: 2: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Alternate register or bit definitions when the module is operating in Host mode. This register is available in Host mode only. TABLE 4-23: File Name U1EP10 U1EP11 U1EP12 U1EP13 U1EP14 U1EP15 U1PWMRRS U1PWMCON Legend: Note 1: 2: Addr 04BE 04C0 04C2 04C4 04C6 04C8 04CC 04CE USB OTG REGISTER MAP (CONTINUED) Bit 15 -- -- -- -- -- -- PWMEN Bit 14 -- -- -- -- -- -- -- Bit 13 -- -- -- -- -- -- -- Bit 12 -- -- -- -- -- -- -- Bit 11 -- -- -- -- -- -- -- Bit 10 -- -- -- -- -- -- -- Bit 9 -- -- -- -- -- -- Bit 8 -- -- -- -- -- -- Bit 7 -- -- -- -- -- -- -- Bit 6 -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- Bit 4 EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS -- Bit 3 EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN -- Bit 2 EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN -- Bit 1 EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL -- Bit 0 EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK -- All Resets 0000 0000 0000 0000 0000 0000 0000 0000 DS39969B-page 64 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY USB Power Supply PWM Duty Cycle Register PWMPOL CNTEN USB Power Supply PWM Period Register -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Alternate register or bit definitions when the module is operating in Host mode. This register is available in Host mode only. TABLE 4-24: File Name ANCFG Legend: Addr 04DE ANCFG REGISTER MAP Bit 15 -- Bit 14 -- Bit 13 -- Bit 12 -- Bit 11 -- Bit 10 -- Bit 9 -- Bit 8 -- Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 VBG6EN Bit 1 VBG2EN Bit 0 VBGEN All Resets 0000 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-25: File Name ANSA(1) ANSB ANSC ANSD ANSE(1) ANSF ANSG Legend: Note 1: 2: Addr 04E0 04E2 04E4 04E6 04E8 04EA 04EC ANSEL REGISTER MAP Bit 15 -- ANSB15 -- -- -- -- -- Bit 14 -- ANSB14 ANSC14 -- -- -- -- Bit 13 -- ANSB13 ANSC13 -- -- -- -- Bit 12 -- ANSB12 -- -- -- -- -- Bit 11 -- ANSB11 -- -- -- -- -- Bit 10 ANSA10(1) ANSB10 -- -- -- -- -- Bit 9 ANSA9(1) ANSB9 -- -- ANSE9(1) -- ANSG9 Bit 8 -- ANSB8 -- -- -- -- ANSG8 Bit 7 ANSA7(1) ANSB7 -- ANSD7 -- -- ANSG7 Bit 6 ANSA6(1) ANSB6 -- ANSD6 -- -- ANSG6 Bit 5 -- ANSB5 -- -- -- -- -- Bit 4 -- ANSB4 ANSC4(1) -- -- -- -- Bit 3 -- ANSB3 -- -- -- -- -- Bit 2 -- ANSB2 -- -- -- -- -- Bit 1 -- ANSB1 -- -- -- -- -- Bit 0 -- ANSB0 -- -- -- ANSF0 -- All Resets(2) 06C0 FFFF 6010 00C0 0200 0001 03C0 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices, read as `0'. Reset values are valid for 100-pin devices only. TABLE 4-26: File Name PMCON1 PMCON2 PMCON3 PMCON4 PMCS1CF PMCS1BS PMCS1MD PMCS2CF PMCS2BS PMCS2MD PMDOUT1 PMDOUT2 PMDIN1 PMDIN2 PMSTAT Legend: Note 1: Addr 0600 0602 0606 0608 060A 060C 060E 0610 0612 0614 0616 0618 061A 061C ENHANCED PARALLEL MASTER/SLAVE PORT REGISTER MAP(1) Bit 15 PMPEN BUSY PTEN15 CSDIS BASE23 ACKM1 CSDIS BASE23 ACKM1 Bit 14 -- -- PTEN14 CSP BASE22 ACKM0 CSP BASE22 ACKM0 Bit 13 PSIDL ERROR PTBE1EN PTEN13 CSPTEN BASE21 AMWAIT2 CSPTEN BASE21 AMWAIT2 Bit 12 ADRMUX1 TIMEOUT PTBE0EN PTEN12 BEP BASE20 AMWAIT1 BEP BASE20 AMWAIT1 Bit 11 ADRMUX0 AMREQ -- PTEN11 -- BASE19 AMWAIT0 -- BASE19 AMWAIT0 Bit 10 -- CURMST AWAITM1 PTEN10 WRSP BASE18 -- WRSP BASE18 -- Bit 9 MODE1 AWAITM0 PTEN9 RDSP BASE17 -- RDSP BASE17 -- Bit 8 MODE0 AWAITE PTEN8 SM BASE16 -- SM BASE16 -- Bit 7 CSF1 -- PTEN7 ACKP BASE15 DWAITB1 ACKP BASE15 DWAITB1 Bit 6 CSF0 PTEN22 PTEN6 PTSZ1 -- PTSZ1 -- Bit 5 ALP PTEN21 PTEN5 PTSZ0 -- PTSZ0 -- Bit 4 ALMODE PTEN20 PTEN4 -- -- DWAITM2 -- -- DWAITM2 Bit 3 -- PTEN19 PTEN3 -- BASE11 -- BASE11 Bit 2 BUSKEEP PTEN18 PTEN2 -- -- -- -- Bit 1 IRQM1 PTEN17 PTEN1 -- -- DWAITE1 -- -- DWAITE1 Bit 0 IRQM0 PTEN16 PTEN0 -- -- DWAITE0 -- -- DWAITE0 All Resets 0000 0000 0000 0000 0000 0200 0000 0000 0600 0000 xxxx xxxx xxxx xxxx OB2E OB1E OB0E 008F 2010 Microchip Technology Inc. DS39969B-page 65 MSTSEL1 MSTSEL0 RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16 0604 PTWREN PTRDEN DWAITB0 DWAITM3 DWAITM1 DWAITM0 DWAITB0 DWAITM3 DWAITM1 DWAITM0 EPMP Data Out Register 1<15:8> EPMP Data Out Register 2<15:8> EPMP Data In Register 1<15:8> EPMP Data In Register 2<15:8> IBF IBOV -- -- IB3F IB2F IB1F IB0F OBE OBUF -- EPMP Data Out Register 1<7:0> EPMP Data Out Register 2<7:0> EPMP Data In Register 1<7:0> EPMP Data In Register 2<7:0> -- OB3E PIC24FJ256DA210 FAMILY -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices, read as `0'. TABLE 4-27: File Name ALRMVAL ALCFGRPT RTCVAL RCFGCAL Legend: Note 1: Addr 0620 0622 0624 0626 REAL-TIME CLOCK AND CALENDAR REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ARPT5 CAL5 ARPT4 CAL4 ARPT3 CAL3 ARPT2 CAL2 ARPT1 CAL1 ARPT0 CAL0 0000 xxxx (Note 1) Alarm Value Register Window Based on ALRMPTR<1:0> ALRMEN RTCEN CHIME -- AMASK3 AMASK2 AMASK1 AMASK0 RTCOE ALRMPTR1 ALRMPTR0 RTCPTR1 RTCPTR0 ARPT7 CAL7 ARPT6 CAL6 RTCC Value Register Window Based on RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. The status of the RCFGCAL register on POR is `0000' and on other Resets is unchanged. DS39969B-page 66 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 4-28: File Name CMSTAT CVRCON CM1CON CM2CON CM3CON Legend: Addr 0630 0632 0634 0636 0638 COMPARATORS REGISTER MAP Bit 15 CMIDL -- CON CON CON Bit 14 -- -- COE COE COE Bit 13 -- -- CPOL CPOL CPOL Bit 12 -- -- -- -- -- -- -- -- -- Bit 11 Bit 10 C3EVT -- -- -- Bit 9 C2EVT CEVT CEVT CEVT Bit 8 C1EVT COUT COUT COUT Bit 7 -- CVREN EVPOL1 EVPOL1 EVPOL1 Bit 6 -- CVROE EVPOL0 EVPOL0 EVPOL0 Bit 5 -- CVRR -- -- -- Bit 4 -- CVRSS CREF CREF CREF Bit 3 -- CVR3 -- -- -- Bit 2 C3OUT CVR2 -- -- -- Bit 1 C2OUT CVR1 CCH1 CCH1 CCH1 Bit 0 C1OUT CVR0 CCH0 CCH0 CCH0 All Resets 0000 0000 0000 0000 0000 CVREFP CVREFM1 CVREFM0 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-29: File Name CRCCON1 CRCCON2 CRCXORL CRCXORH CRCDATL CRCDATH CRCWDATL CRCWDATH Legend: Addr 0640 0642 0644 0646 0648 064A 064C 064E CRC REGISTER MAP Bit 15 CRCEN -- X15 X31 Bit 14 -- -- X14 X30 Bit 13 CSIDL -- X13 X29 Bit 12 VWORD4 DWIDTH4 X12 X28 Bit 11 VWORD3 DWIDTH3 X11 X27 Bit 10 VWORD2 DWIDTH2 X10 X26 Bit 9 VWORD1 DWIDTH1 X9 X25 Bit 8 VWORD0 DWIDTH0 X8 X24 Bit 7 CRCFUL -- X7 X23 Bit 6 CRCMPT -- X6 X22 Bit 5 CRCISEL -- X5 X21 Bit 4 CRCGO PLEN4 X4 X20 Bit 3 LENDIAN PLEN3 X3 X19 Bit 2 -- PLEN2 X2 X18 Bit 1 -- PLEN1 X1 X17 Bit 0 -- PLEN0 -- X16 All Resets 0040 0000 0000 0000 0000 0000 0000 0000 CRC Data Input Register Low CRC Data Input Register High CRC Result Register Low CRC Result Register High -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 4-30: File Name RPINR0 RPINR1 RPINR2 RPINR3 RPINR4 RPINR7 RPINR8 RPINR9 RPINR10 RPINR11 RPINR15 RPINR17 RPINR18 RPINR19 RPINR20 RPINR21 RPINR22 RPINR23 RPINR27 RPINR28 RPINR29 Legend: Note 1: Addr 0680 0682 0684 0686 0688 068E 0690 0692 0694 0696 069E 06A2 06A4 06A6 06A8 06AA 06AC 06AE 06B6 06B8 06BA PERIPHERAL PIN SELECT REGISTER MAP Bit 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 13 INT1R5 INT3R5 -- T3CKR5 T5CKR5 IC2R5 IC4R5 IC6R5 IC8R5 OCFBR5 IC9R5 U3RXR5 U1CTSR5 U2CTSR5 SCK1R5 U3CTSR5 SCK2R5 -- U4CTSR5 SCK3R5 -- Bit 12 INT1R4 INT3R4 -- T3CKR4 T5CKR4 IC2R4 IC4R4 IC6R4 IC8R4 OCFBR4 IC9R4 U3RXR4 U1CTSR4 U2CTSR4 SCK1R4 U3CTSR4 SCK2R4 -- U4CTSR4 SCK3R4 -- Bit 11 INT1R3 INT3R3 -- T3CKR3 T5CKR3 IC2R3 IC4R3 IC6R3 IC8R3 OCFBR3 IC9R3 U3RXR3 U1CTSR3 U2CTSR3 SCK1R3 U3CTSR3 SCK2R3 -- U4CTSR3 SCK3R3 -- Bit 10 INT1R2 INT3R2 -- T3CKR2 T5CKR2 IC2R2 IC4R2 IC6R2 IC8R2 OCFBR2 IC9R2 U3RXR2 U1CTSR2 U2CTSR2 SCK1R2 U3CTSR2 SCK2R2 -- U4CTSR2 SCK3R2 -- Bit 9 INT1R1 INT3R1 -- T3CKR1 T5CKR1 IC2R1 IC4R1 IC6R1 IC8R1 OCFBR1 IC9R1 U3RXR1 U1CTSR1 U2CTSR1 SCK1R1 U3CTSR1 SCK2R1 -- U4CTSR1 SCK3R1 -- Bit 8 INT1R0 INT3R0 -- T3CKR0 T5CKR0 IC2R0 IC4R0 IC6R0 IC8R0 OCFBR0 IC9R0 U3RXR0 U1CTSR0 U2CTSR0 SCK1R0 U3CTSR0 SCK2R0 -- U4CTSR0 SCK3R0 -- Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- INT2R5 INT4R5 T2CKR5 T4CKR5 IC1R5 IC3R5 IC5R5 IC7R5 OCFAR5 -- -- U1RXR5 U2RXR5 SDI1R5 SS1R5 SDI2R5 SS2R5 U4RXR5 SDI3R5 SS3R5 Bit 4 -- INT2R4 INT4R4 T2CKR4 T4CKR4 IC1R4 IC3R4 IC5R4 IC7R4 OCFAR4 -- -- U1RXR4 U2RXR4 SDI1R4 SS1R4 SDI2R4 SS2R4 U4RXR4 SDI3R4 SS3R4 Bit 3 -- INT2R3 INT4R3 T2CKR3 T4CKR3 IC1R3 IC3R3 IC5R3 IC7R3 OCFAR3 -- -- U1RXR3 U2RXR3 SDI1R3 SS1R3 SDI2R3 SS2R3 U4RXR3 SDI3R3 SS3R3 Bit 2 -- INT2R2 INT4R2 T2CKR2 T4CKR2 IC1R2 IC3R2 IC5R2 IC7R2 OCFAR2 -- -- U1RXR2 U2RXR2 SDI1R2 SS1R2 SDI2R2 SS2R2 U4RXR2 SDI3R2 SS3R2 Bit 1 -- INT2R1 INT4R1 T2CKR1 T4CKR1 IC1R1 IC3R1 IC5R1 IC7R1 OCFAR1 -- -- U1RXR1 U2RXR1 SDI1R1 SS1R1 SDI2R1 SS2R1 U4RXR1 SDI3R1 SS3R1 Bit 0 -- INT2R0 INT4R0 T2CKR0 T4CKR0 IC1R0 IC3R0 IC5R0 IC7R0 OCFAR0 -- -- U1RXR0 U2RXR0 SDI1R0 SS1R0 SDI2R0 SS2R0 U4RXR0 SDI3R0 SS3R0 All Resets 3F00 3F3F 003F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F00 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 003F 3F3F 3F3F 003F 2010 Microchip Technology Inc. DS39969B-page 67 PIC24FJ256DA210 FAMILY -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bits are unimplemented in 64-pin devices; read as `0'. TABLE 4-30: File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 RPOR8 RPOR9 RPOR10 RPOR11 RPOR12 RPOR13 RPOR14 RPOR15(1) Legend: Note 1: Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE 06D0 06D2 06D4 06D6 06D8 06DA 06DC 06DE PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) Bit 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 13 RP1R5 RP3R5 RP5R5(1) RP7R5 RP9R5 RP11R5 RP13R5 RP15R5(1) RP17R5 RP19R5 RP21R5 RP23R5 RP25R5 RP27R5 RP29R5 RP31R5(1) Bit 12 RP1R4 RP3R4 RP5R4(1) RP7R4 RP9R4 RP11R4 RP13R4 RP15R4(1) RP17R4 RP19R4 RP21R4 RP23R4 RP25R4 RP27R4 RP29R4 RP31R4(1) Bit 11 RP1R3 RP3R3 RP5R3(1) RP7R3 RP9R3 RP11R3 RP13R3 RP15R3(1) RP17R3 RP19R3 RP21R3 RP23R3 RP25R3 RP27R3 RP29R3 RP31R3(1) Bit 10 RP1R2 RP3R2 RP5R2(1) RP7R2 RP9R2 RP11R2 RP13R2 RP15R2(1) RP17R2 RP19R2 RP21R2 RP23R2 RP25R2 RP27R2 RP29R2 RP31R2(1) Bit 9 RP1R1 RP3R1 RP5R1(1) RP7R1 RP9R1 RP11R1 RP13R1 RP15R1(1) RP17R1 RP19R1 RP21R1 RP23R1 RP25R1 RP27R1 RP29R1 RP31R1(1) Bit 8 RP1R0 RP3R0 RP5R0(1) RP7R0 RP9R0 RP11R0 RP13R0 RP15R0(1) RP17R0 RP19R0 RP21R0 RP23R0 RP25R0 RP27R0 RP29R0 RP31R0(1) Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 RP0R5 RP2R5 RP4R5 RP6R5 RP8R5 RP10R5 RP12R5 RP14R5 RP16R5 RP18R5 RP20R5 RP22R5 RP24R5 RP26R5 RP28R5 Bit 4 RP0R4 RP2R4 RP4R4 RP6R4 RP8R4 RP10R4 RP12R4 RP14R4 RP16R4 RP18R4 RP20R4 RP22R4 RP24R4 RP26R4 RP28R4 Bit 3 RP0R3 RP2R3 RP4R3 RP6R3 RP8R3 RP10R3 RP12R3 RP14R3 RP16R3 RP18R3 RP20R3 RP22R3 RP24R3 RP26R3 RP28R3 Bit 2 RP0R2 RP2R2 RP4R2 RP6R2 RP8R2 RP10R2 RP12R2 RP14R2 RP16R2 RP18R2 RP20R2 RP22R2 RP24R2 RP26R2 RP28R2 Bit 1 RP0R1 RP2R1 RP4R1 RP6R1 RP8R1 RP10R1 RP12R1 RP14R1 RP16R1 RP18R1 RP20R1 RP22R1 RP24R1 RP26R1 RP28R1 Bit 0 RP0R0 RP2R0 RP4R0 RP6R0 RP8R0 RP10R0 RP12R0 RP14R0 RP16R0 RP18R0 RP20R0 RP22R0 RP24R0 RP26R0 RP28R0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DS39969B-page 68 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY RP30R5(1) RP30R4(1) RP30R3(1) RP30R2(1) RP30R1(1) RP30R0(1) -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bits are unimplemented in 64-pin devices; read as `0'. 2010 Microchip Technology Inc. DS39969B-page 69 TABLE 4-31: File Name G1CMDL G1CMDH G1CON1 G1STAT G1IE G1IR G1W1ADRL G1W1ADRH G1W2ADRL G1W2ADRH G1PUW G1PUH G1DPADRL G1DPADRH G1DPW G1DPH G1DPWT G1DPHT G1CON2 G1CON3 G1ACTDA G1HSYNC G1VSYNC G1DBLCON G1CLUT G1CLUTWR G1CLUTRD G1MRGN G1CHRX G1CHRY G1IPU G1DBEN Legend: Addr 0700 0702 0704 0706 0708 070A 070C 070E 0710 0712 0714 0716 0718 071A 071C 071E 0720 0722 0724 0726 0728 072A 072C 072E 0730 0732 0734 0736 0738 073A 073C 073E GRAPHICS REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 PUBPP1 RCCIE RCCIF PUBPP0 CHRIE CHRIF GCMDCNT4 GCMDCNT3 VMRGN VMRGNIE VMRGNIF HMRGN HMRGNIE HMRGNIF GCMDCNT2 GCMDCNT1 GCMDCNT0 CMDLV CMDLVIE CMDLVIF CMDFUL CMDMPT CMDFULIE CMDMPTIE CMDFULIF CMDMPTIF 0000 0000 0000 0000 0000 GPU Work Area 1 Start Address Register<23:16> GPU Work Area 2 Start Address Register<23:16> GPU Work Area Width Register GPU Work Area Height Register Display Buffer Start Address Register<15:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DPTEST1 DPPINOE DPTEST0 DPPOWER DPBPP2 -- -- -- Display Buffer Start Address Register<23:16> Display Frame Width Register Display Frame Height Register Display Total Width Register Display Total Height Register DPBPP1 DPBPP0 -- -- DPPWROE DPMODE2 DPENOE DPMODE1 DPVSOE DPMODE0 DPHSOE DPCLKPOL DPENPOL DPVSPOL DPHSPOL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Horizontal Blanking Advance Register Current Character X-Coordinate Position Register Current Character Y-Coordinate Position Register -- GDBEN10 -- GDBEN9 -- GDBEN8 -- GDBEN7 -- GDBEN6 HUFFERR GDBEN5 BLCKERR GDBEN4 LENERR GDBEN3 WRAPERR GDBEN2 IPUDONE GDBEN1 BFINAL GDBEN0 0000 0000 0000 0000 0000 Graphics Command Register<15:0> Graphics Command Register<31:16> G1EN PUBUSY PUIE PUIF -- -- -- -- -- -- -- -- -- -- -- -- G1SIDL -- -- -- -- -- -- -- GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PUBPP2 IPUBUSY IPUIE IPUIF RCCBUSY CHRBUSY GPU Work Area 1 Start Address Register<15:0> GPU Work Area 2 Start Address Register<15:0> PIC24FJ256DA210 FAMILY DPGWDTH1 DPGWDTH0 DPSTGER1 DPSTGER0 Number of Lines Before the First Active Line Register HSYNC Pulse-Width Configuration Register VSYNC Pulse-Width Configuration Register Vertical Blanking Start to First Displayed Line Configuration Regsiter CLUTEN CLUTBUSY -- -- -- -- CLUTTRD CLUTRWEN Number of Pixels Before the First Active PIxel Register HSYNC Start Delay Configuration Register VSYNC Start Delay Configuration Register Horizontal Blanking Start to First Displayed Line Configuration Regsiter Color Look-Up Table Memory Address Register Color Look-up Table Memory Write Data Register Color Look-up Table Memory Read Data Register Vertical Blanking Advance Register -- -- -- GDBEN15 -- -- -- GDBEN14 -- -- -- GDBEN13 -- -- -- GDBEN12 -- -- -- GDBEN11 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. DS39969B-page 70 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 4-32: File Name RCON OSCCON CLKDIV CLKDIV2 OSCTUN REFOCON Legend: Note 1: 2: Addr 0740 0742 0744 0746 0748 074E SYSTEM REGISTER MAP Bit 15 TRAPR -- ROI GCLKDIV6 -- ROEN Bit 14 IOPUWR COSC2 DOZE2 GCLKDIV5 -- -- Bit 13 -- COSC1 DOZE1 GCLKDIV4 -- ROSSLP Bit 12 -- COSC0 DOZE0 GCLKDIV3 -- ROSEL Bit 11 -- -- DOZEN GCLKDIV2 -- RODIV3 Bit 10 -- NOSC2 RCDIV2 GCLKDIV1 -- RODIV2 Bit 9 CM NOSC1 RCDIV1 GCLKDIV0 -- RODIV1 Bit 8 VREGS NOSC0 RCDIV0 -- -- RODIV0 Bit 7 EXTR CLKLOCK CPDIV1 -- -- -- Bit 6 SWR IOLOCK CPDIV0 -- -- -- Bit 5 SWDTEN LOCK PLLEN -- TUN5 -- Bit 4 WDTO -- G1CLKSEL -- TUN4 -- Bit 3 SLEEP CF -- -- TUN3 -- Bit 2 IDLE POSCEN -- -- TUN2 -- Bit 1 BOR SOSCEN -- -- TUN1 -- Bit 0 POR OSWEN -- -- TUN0 -- All Resets Note 1 Note 2 0100 0000 0000 0000 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. The Reset value of the RCON register is dependent on the type of Reset event. See Section 6.0 "Resets" for more information. The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 8.0 "Oscillator Configuration" for more information. TABLE 4-33: File Name NVMCON NVMKEY Legend: Note 1: Addr 0760 0766 NVM REGISTER MAP Bit 15 WR -- Bit 14 WREN -- Bit 13 WRERR -- Bit 12 -- -- Bit 11 -- -- Bit 10 -- -- Bit 9 -- -- Bit 8 -- -- Bit 7 -- Bit 6 ERASE Bit 5 -- Bit 4 -- Bit 3 NVMOP3 Bit 2 NVMOP2 Bit 1 NVMOP1 Bit 0 NVMOP0 All Resets 0000(1) 0000 NVMKEY Register<7:0> -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 4-34: File Name PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 Legend: Note 1: Addr 0770 0772 0774 0776 0778 077A PMD REGISTER MAP Bit 15 T5MD IC8MD -- -- -- -- Bit 14 T4MD IC7MD -- -- -- -- Bit 13 T3MD IC6MD -- -- -- -- Bit 12 T2MD IC5MD -- -- -- -- Bit 11 T1MD IC4MD -- -- -- -- Bit 10 -- IC3MD CMPMD -- -- -- Bit 9 -- IC2MD RTCCMD -- -- -- Bit 8 -- IC1MD PMPMD(1) -- IC9MD -- Bit 7 I2C1MD OC8MD CRCMD -- -- -- Bit 6 U2MD OC7MD -- UPWMMD -- GFX1MD Bit 5 U1MD OC6MD -- U4MD -- -- Bit 4 SPI2MD OC5MD -- -- -- -- Bit 3 SPI1MD OC4MD U3MD -- -- Bit 2 -- OC3MD I2C3MD -- -- Bit 1 -- OC2MD I2C2MD LVDMD -- -- Bit 0 ADC1MD OC1MD -- USB1MD OC9MD SPI3MD All Resets 0000 0000 0000 0000 0000 0000 REFOMD CTMUMD -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices, read as `0'. PIC24FJ256DA210 FAMILY 4.2.5 EXTENDED DATA SPACE (EDS) The enhancement of the data space in PIC24FJ256DA210 family devices has been accomplished by a new technique, called the Extended Data Space (EDS). The EDS includes any additional internal extended data memory not accessible by the lower 32 Kbytes data address space, any external memory through EPMP and the Program Space Visibility (PSV). The extended data space is always accessed through the EDS window, the upper half of data space. The entire extended data space is organized into EDS pages, each having 32 Kbytes of data. Mapping of the EDS page into the EDS window is done using the Data Space Read register (DSRPAG<9:0>) for read operations and Data Space Write register (DSWPAG<8:0>) for write operations. Figure 4-4 displays the entire EDS space. Note: Accessing Page 0 in the EDS window will generate an address error trap as Page 0 is the base data memory (data locations, 0x0800 to 0x7FFF, in the lower data space). FIGURE 4-4: EXTENDED DATA SPACE Special 0x0000 Function Registers 0x0800 30 KB Data Memory EDS Space 0x8000 0x008000 0x018000 Internal Extended Memory(1) 0x0187FE 0x018800 External Memory Access using EPMP(2) 0xFF8000 0x000000 0x7F8000 0x000001 0x7F8001 32 KB EDS Window Internal Extended Memory(1) External Memory Access using EPMP(2) Program Space Access Program Space Access Program Space Access Program Space Access 0xFFFE 0x00FFFE DSxPAG = 0x001 0x01FFFE DSxPAG = 0x003 0xFFFFFE DSx PAG = 0x1FF 0x007FFE DSRPAG = 0x200 0x7FFFFE DSRPAG = 0x2FF 0x007FFF DSRPAG = 0x300 0x7FFFFF DSRPAG = 0x3FF Extended SRAM(1) (66 KB) EPMP Memory Space(2) Note 1: 2: Program Memory Available only in PIC24FJXXXDA2XX devices. In the PIC24FJXXXDA110 devices, this space can be used to access external memory using EPMP. Available only in PIC24FJXXXDAX10 devices (100-pin). 2010 Microchip Technology Inc. DS39969B-page 71 PIC24FJ256DA210 FAMILY 4.2.5.1 Data Read from EDS Space In order to read the data from the EDS space, first, an Address Pointer is set up by loading the required EDS page number into the DSRPAG register and assigning the offset address to one of the W registers. Once the above assignment is done, the EDS window is enabled by setting bit 15 of the working register, assigned with the offset address; then, the contents of the pointed EDS location can be read. Figure 4-5 illustrates how the EDS space address is generated for read operations. FIGURE 4-5: EDS ADDRESS GENERATION FOR READ OPERATIONS Select 9 8 DSRPAG Reg 9 Bits 1 0 Wn 15 Bits 24-Bit EA 0 = Extended SRAM and EPMP Wn<0> is Byte Select When the Most Significant bit (MSBs) of EA is `1' and DSRPAG<9> = 0, the lower 9 bits of DSRPAG are concatenated to the lower 15 bits of EA to form a 24-bit EDS space address for read operations. Example 4-1 shows how to read a byte, word and double-word from EDS. Note: All read operations from EDS space have an overhead of one instruction cycle. Therefore, a minimum of two instruction cycles is required to complete an EDS read. EDS reads under the REPEAT instruction; the first two accesses take three cycles and the subsequent accesses take one cycle. EXAMPLE 4-1: EDS READ CODE IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0002 , w0 mov w0 , DSRPAG ;page 2 is selected for read mov #0x0800 , w1 ;select the location (0x800) to be read bset w1 , #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++] , w2 ;read Low byte mov.b [w1++] , w3 ;read High byte ;Read a word from the selected location mov [w1] , w2 ; ;Read Double - word from the selected location mov.d [w1] , w2 ;two word read, stored in w2 and w3 DS39969B-page 72 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 4.2.5.2 Data Write into EDS Space In order to write data to EDS space, such as in EDS reads, an Address Pointer is set up by loading the required EDS page number into the DSWPAG register, and assigning the offset address to one of the W registers. Once the above assignment is done, then the EDS window is enabled by setting bit 15 of the working register, assigned with the offset address, and the accessed location can be written. Figure 4-2 illustrates how the EDS space address is generated for write operations. FIGURE 4-6: EDS ADDRESS GENERATION FOR WRITE OPERATIONS Select 8 DSWPAG Reg 9 Bits 1 0 Wn 15 Bits 24-Bit EA Wn<0> is Byte Select When the MSBs of EA is `1', the lower 9 bits of DSWPAG are concatenated to the lower 15 bits of EA to form a 24-bit EDS address for write operations. Example 4-2 shows how to write a byte, word and double-word to EDS. EXAMPLE 4-2: EDS WRITE CODE IN ASSEMBLY ; Set the EDS page where the data to be written mov #0x0002 , w0 mov w0 , DSWPAG ;page 2 is selected for write mov #0x0800 , w1 ;select the location (0x800) to be written bset w1 , #15 ;set the MSB of the base address, enable EDS mode ;Write a byte to the selected location mov #0x00A5 , w2 mov #0x003C , w3 mov.b w2 , [w1++] ;write Low byte mov.b w3 , [w1++] ;write High byte ;Write a word to the selected location mov #0x1234 , w2 ; mov w2 , [w1] ; ;Write a Double - word to the selected location mov #0x1122 , w2 mov #0x4455 , w3 mov.d w2 , [w1] ;2 EDS writes 2010 Microchip Technology Inc. DS39969B-page 73 PIC24FJ256DA210 FAMILY The page registers (DSRPAG/DSWPAG) do not update automatically while crossing a page boundary, when the rollover happens from 0xFFFF to 0x8000. While developing code in assembly, care must be taken to update the page registers when an Address Pointer crosses the page boundary. The `C' compiler keeps track of the addressing, and increments or decrements the page registers accordingly while accessing contiguous data memory locations. Note 1: All write operations to EDS are executed in a single cycle. 2: Use of Read/Modify/Write operation on any EDS location under a REPEAT instruction is not supported. For example, BCLR, BSW, BTG, RLC f, RLNC f, RRC f, RRNC f, ADD f, SUB f, SUBR f, AND f, IOR f, XOR f, ASR f, ASL f. 3: Use the DSRPAG register while performing Read/Modify/Write operation. TABLE 4-35: EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES DSWPAG (Data Space Write Register) x(1) Source/Destination Address while Indirect Addressing 0x0000 to 0x1FFF 0x2000 to 0x7FFF 24-Bit EA Pointing to EDS 0x000000 to 0x001FFF 0x002000 to 0x007FFF 0x008000 to 0x00FFFE 0x010000 to 0x017FFE 0x018000 to 0x0187FE Comment Near data space(2) DSRPAG (Data Space Read Register) x(1) 0x001 0x002 0x003 0x001 0x002 0x003 0x8000 to 0xFFFF 32 Kbytes on each page Only 2 Kbytes of extended SRAM on this page 0x004 * * * 0x1FF 0x000 0x004 * * * 0x1FF 0x000 Note 1: 2: 3: 4: Address error trap(3) If the source/destination address is below 0x8000, the DSRPAG and DSWPAG registers are not considered. This data space can also be accessed by Direct Addressing. When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is `0', an address error trap will occur. EPMP memory space can start from location, 0x008000, in the parts with 24 Kbytes of data memory (PIC24FJXXXDA1XX) 0x018800 to 0x027FFE * * * 0xFF8000 to 0xFFFFFE Invalid Address EPMP memory space(4) DS39969B-page 74 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 4.2.6 SOFTWARE STACK 4.3 Apart from its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer (SSP). The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-7. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be accessed during operation: * Using table instructions to access individual bytes or words anywhere in the program space * Remapping a portion of the program space into the data space (program space visibility) Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word. The Stack Pointer Limit Value register (SPLIM), associated with the Stack Pointer, sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to `0' as all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the SFR space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. 4.3.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Memory Page Address register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the MSBs of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). For remapping operations, the 10-bit Extended Data Space Read register (DSRPAG) is used to define a 16K word page in the program space. When the Most Significant bit (MSb) of the EA is `1', and the MSb (bit 9) of DSRPAG is `1', the lower 8 bits of DSRPAG are concatenated with the lower 15 bits of the EA to form a 23-bit program space address. The DSRPAG<8> bit decides whether the lower word (when bit is `0') or the higher word (when bit is `1') of program memory is mapped. Unlike table operations, this strictly limits remapping operations to the user memory area. Table 4-36 and Figure 4-8 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. FIGURE 4-7: 0000h 15 CALL STACK FRAME 0 Stack Grows Towards Higher Address PC<15:0> 000000000 PC<22:16> W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] 2010 Microchip Technology Inc. DS39969B-page 75 PIC24FJ256DA210 FAMILY TABLE 4-36: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note 1: 2: User 0 0 Program Space Address <23> 0 TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx DSRPAG<7:0>(2) xxxx xxxx <22:16> <15> PC<22:1> 0xx xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx <14:1> <0> 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Data EA<15> is always `1' in this case, but is not used in calculating the program space address. Bit 15 of the address is DSRPAG<0>. DSRPAG<9> is always `1' in this case. DSRPAG<8> decides whether the lower word or higher word of program memory is read. When DSRPAG<8> is `0', the lower word is read and when it is `1', the higher word is read. FIGURE 4-8: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 0 Program Counter 23 Bits 0 Program Counter EA Table Operations(2) 1/0 TBLPAG 8 Bits 24 Bits 16 Bits 1/0 Select 1 Program Space Visibility(1) (Remapping) 0 1-Bit DSRPAG<7:0> 8 Bits 23 Bits EA 1/0 15 Bits User/Configuration Space Select Byte Select Note 1: 2: DSRPAG<8> acts as word select. DSRPAG<9> should always be `1' to map program memory to data memory. The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the lower word. Table read operations are permitted in the configuration memory space. DS39969B-page 76 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the `phantom' byte, will always be `0'. In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be `0' when the upper `phantom' byte is selected (byte select = 1). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two, 16-bit word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is `1'; the lower byte is selected when it is `0'. In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are described in Section 5.0 "Flash Program Memory". For all table operations, the area of program memory space to be accessed is determined by the Table Memory Page Address register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, where Device IDs are located. Table write operations are not allowed. FIGURE 4-9: TBLPAG 02 ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space Data EA<15:0> 23 15 0 000000h 00000000 020000h 030000h 00000000 00000000 00000000 `Phantom' Byte 23 16 8 0 TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 800000h 2010 Microchip Technology Inc. DS39969B-page 77 PIC24FJ256DA210 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING EDS The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs when the MSb of EA is `1' and the DSRPAG<9> is also `1'. The lower 8 bits of DSRPAG are concatenated to the Wn<14:0> bits to form a 23-bit EA to access program memory. The DSRPAG<8> decides which word should be addressed; when the bit is `0', the lower word and when `1', the upper word of the program memory is accessed. The entire program memory is divided into 512 EDS pages, from 0x200 to 0x3FF, each consisting of 16K words of data. Pages, 0x200 to 0x2FF, correspond to the lower words of the program memory, while 0x300 to 0x3FF correspond to the upper words of the program memory. Using this EDS technique, the entire program memory can be accessed. Previously, the access to the upper word of the program memory was not supported. Table 4-37 provides the corresponding 23-bit EDS address for program memory with EDS page and source addresses. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV, which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: * Execution in the first iteration * Execution in the last iteration * Execution prior to exiting the loop due to an interrupt * Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. TABLE 4-37: EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES Source Address while Indirect Addressing 23-Bit EA Pointing to EDS 0x000000 to 0x007FFE * * * 0x7F8000 to 0x7FFFFE 0x000001 to 0x007FFF * * * 0x7F8001 to 0x7FFFFF Comment DSRPAG (Data Space Read Register) 0x200 * * * 0x2FF 0x300 * * * 0x3FF Lower words of 4M program instructions; (8 Mbytes) for read operations only. Note 1: Upper words of 4M program instructions (4 Mbytes remaining, 4 Mbytes are phantom bytes) for read operations only. 0x000 Invalid Address Address error trap(1) When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is `0', an address error trap will occur. 0x8000 to 0xFFFF DS39969B-page 78 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD When DSRPAG<9:8> = 10 and EA<15> = 1 Program Space DSRPAG 202h 23 15 0 000000h 010000h 017FFEh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... Data Space 0000h Data EA<14:0> 8000h EDS Window ...while the lower 15 bits of the EA specify an exact address within the EDS area. This corresponds exactly to the same lower 15 bits of the actual program space address. FFFFh 7FFFFEh FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS HIGHER WORD When DSRPAG<9:8> = 11 and EA<15> = 1 Program Space DSRPAG 302h 23 15 0 000000h 010001h 017FFFh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... Data Space 0000h Data EA<14:0> 8000h EDS Window FFFFh 7FFFFEh ...while the lower 15 bits of the EA specify an exact address within the EDS area. This corresponds exactly to the same lower 15 bits of the actual program space address. 2010 Microchip Technology Inc. DS39969B-page 79 PIC24FJ256DA210 FAMILY EXAMPLE 4-3: EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0202 , w0 mov w0 , DSRPAG ;page 0x202, consisting lower words, is selected for read mov #0x000A , w1 ;select the location (0x0A) to be read bset w1 , #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++] , w2 ;read Low byte mov.b [w1++] , w3 ;read High byte ;Read a word from the selected location mov [w1] , w2 ; ;Read Double - word from the selected location mov.d [w1] , w2 ;two word read, stored in w2 and w3 DS39969B-page 80 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 4. "Program Memory" (DS39715). The information in this data sheet supersedes the information in the FRM. microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time and erase program memory in blocks of 512 instructions (1536 bytes) at a time. 5.1 The PIC24FJ256DA210 family of devices contains internal Flash program memory for storing and executing application code. The program memory is readable, writable and erasable. The Flash can be programmed in four ways: * * * * In-Circuit Serial ProgrammingTM (ICSPTM) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP) Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG<7:0> bits and the Effective Address (EA) from a W register, specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ICSP allows a PIC24FJ256DA210 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (named PGECx and PGEDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 Bits 16 Bits User/Configuration Space Select 24-Bit EA Byte Select 2010 Microchip Technology Inc. DS39969B-page 81 PIC24FJ256DA210 FAMILY 5.2 RTSP Operation 5.3 JTAG Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 64 TBLWT instructions are required to write the full row of memory. To ensure that no data is corrupted during a write, any unused address should be programmed with FFFFFFh. This is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows which were not rewritten. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing is not recommended. The PIC24F family supports JTAG boundary scan. Boundary scan can improve the manufacturing process by verifying pin to PCB connectivity. 5.4 Enhanced In-Circuit Serial Programming Enhanced In-Circuit Serial Programming uses an on-board bootloader, known as the program executive, to manage the programming process. Using an SPI data frame format, the program executive can erase, program and verify program memory. For more information on Enhanced ICSP, see the device programming specification. 5.5 Control Registers There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and when the programming cycle starts. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 5.6 "Programming Operations" for further details. 5.6 Programming Operations All of the table write operations are single-word writes (2 instruction cycles), because only the buffers are written. A programming cycle is required for programming each row. A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. DS39969B-page 82 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 5-1: R/S-0, HC(1) WR bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR HC = Hardware Clearable bit bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive WREN: Write Enable bit(1) 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as `0' ERASE: Erase/Program Enable bit(1) 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command Unimplemented: Read as `0' NVMOP<3:0>: NVM Operation Select bits(1,2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) These bits can only be reset on POR. All other combinations of NVMOP<3:0> are unimplemented. Available in ICSPTM mode only; refer to the device programming specification. S = Settable bit W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 -- U-0 -- R/W-0(1) NVMOP3(2) R/W-0(1) NVMOP2(2) R/W-0(1) NVMOP1(2) NVMCON: FLASH MEMORY CONTROL REGISTER R-0, HSC(1) WRERR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0(1) NVMOP0(2) bit 0 WREN R/W-0(1) bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: 2: 3: 2010 Microchip Technology Inc. DS39969B-page 83 PIC24FJ256DA210 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON<3:0>) to `0010' to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-3). Write the program block to Flash memory: a) Set the NVMOP bits to `0001' to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-4. EXAMPLE 5-1: ERASING A PROGRAM MEMORY BLOCK (ASSEMBLY LANGUAGE CODE) ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize Program Memory (PM) Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA<15:0> pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV.B #0x55, W0 MOV W0, NVMKEY ; Write the 0x55 key MOV.B #0xAA, W1 ; MOV W1, NVMKEY ; Write the 0xAA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS39969B-page 84 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY BLOCK (`C' LANGUAGE CODE) // C example using MPLAB C30 unsigned long progAddr = 0xXXXXXX; // Address of row to write unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVMCON asm("DISI #5"); // Block all interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // check function to perform unlock // sequence and set WR EXAMPLE 5-3: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] * * * ; 63rd_program_word MOV #LOW_WORD_63, W2 ; MOV #HIGH_BYTE_63, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0] EXAMPLE 5-4: DISI MOV.B MOV MOV.B MOV BSET NOP NOP BTSC BRA #5 INITIATING A PROGRAMMING SEQUENCE ; Block all interrupts with priority <7 ; for next 5 instructions ; ; ; ; ; Write the 0x55 key Write the 0xAA key Start the programming sequence Required delays #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR NVMCON, #15 $-2 ; and wait for it to be ; completed 2010 Microchip Technology Inc. DS39969B-page 85 PIC24FJ256DA210 FAMILY 5.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be programmed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes (MSB) of the Flash address. The TBLWTL and TBLWTH instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to `0011'. The write is performed by executing the unlock sequence and setting the WR bit (see Example 5-5). An equivalent procedure in `C' compiler, using the MPLAB C30 compiler and built-in hardware functions is shown in Example 5-6. EXAMPLE 5-5: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY ; Setup a pointer to data Program Memory MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ;Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address MOV MOV TBLWTL TBLWTH #LOW_WORD_N, W2 #HIGH_BYTE_N, W3 W2, [W0] W3, [W0++] ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; Setup NVMCON for programming one word to data Program Memory MOV #0x4003, W0 ; MOV W0, NVMCON ; Set NVMOP bits to 0011 DISI MOV.B MOV MOV.B MOV BSET NOP NOP #5 #0x55, W0 W0, NVMKEY #0xAA, W0 W0, NVMKEY NVMCON, #WR ; Disable interrupts while the KEY sequence is written ; Write the key sequence ; Start the write cycle ; Required delays EXAMPLE 5-6: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY (`C' LANGUAGE CODE) // C example using MPLAB C30 unsigned int offset; unsigned long progAddr = 0xXXXXXX; unsigned int progDataL = 0xXXXX; unsigned char progDataH = 0xXX; //Set up NVMCON for word programming NVMCON = 0x4003; // Address of word to program // Data to program lower word // Data to program upper byte // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); // Write to address low word __builtin_tblwth(offset, progDataH); // Write to upper byte asm("DISI #5"); // Block interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // C30 function to perform unlock // sequence and set WR DS39969B-page 86 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 6.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 7. "Reset" (DS39712). The information in this data sheet supersedes the information in the FRM. Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: * * * * * * * * * POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A POR will clear all bits, except for the BOR and POR (RCON<1:0>) bits, which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this data sheet. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. A simplified block diagram of the Reset module is shown in Figure 6-1. FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise Detect VDD Brown-out Reset BOR POR SYSRST Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register 2010 Microchip Technology Inc. DS39969B-page 87 PIC24FJ256DA210 FAMILY REGISTER 6-1: R/W-0, HS TRAPR bit 15 R/W-0, HS EXTR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HS SWR R/W-0, HS SWDTEN(2) R/W-0, HS WDTO R/W-0, HS SLEEP R/W-0, HS IDLE R/W-1, HS BOR RCON: RESET CONTROL REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- R/W-0, HS CM R/W-0 VREGS(3) bit 8 R/W-1, HS POR bit 0 R/W-0, HS IOPUWR TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register is used as an Address Pointer and caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as `0' CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred VREGS: Voltage Regulator Standby Enable bit(3) 1 = Program memory and regulator remain active during Sleep/Idle 0 = Program memory power is removed and regulator goes to standby during Seep/Idle EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 Note 1: 2: 3: DS39969B-page 88 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 6-1: bit 2 RCON: RESET CONTROL REGISTER(1) (CONTINUED) IDLE: Wake-up From Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. bit 1 bit 0 Note 1: 2: 3: TABLE 6-1: RESET FLAG BIT OPERATION Setting Event Trap Conflict Event Illegal Opcode or Uninitialized W Register Access Configuration Mismatch Reset MCLR Reset RESET Instruction WDT Time-out PWRSAV #0 Instruction PWRSAV #1 Instruction POR, BOR POR Clearing Event POR POR POR POR POR CLRWDT, PWRSAV Instruction, POR POR POR -- -- Flag Bit TRAPR (RCON<15>) IOPUWR (RCON<14>) CM (RCON<9>) EXTR (RCON<7>) SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note: All Reset flag bits may be set or cleared by the user software. 2010 Microchip Technology Inc. DS39969B-page 89 PIC24FJ256DA210 FAMILY 6.1 Special Function Register Reset States 6.3 Clock Source Selection at Reset Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSC bits in Flash Configuration Word 2 (CW2) (see Table 6-2). The RCFGCAL and NVMCON registers are only affected by a POR. If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table 6-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to the "PIC24F Family Reference Manual", Section 8.0 "Oscillator Configuration" for further details. TABLE 6-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Clock Source Determinant FNOSC Configuration bits (CW2<10:8>) COSC Control bits (OSCCON<14:12>) Reset Type POR BOR MCLR WDTO SWR 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the system Reset signal, SYSRST, is released after the POR delay time expires. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The Fail-Safe Clock Monitor (FSCM) delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. DS39969B-page 90 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 6-3: Reset Type POR(7) RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Clock Source EC ECPLL XT, HS, SOSC XTPLL, HSPLL FRC, FRCDIV FRCPLL LPRC EC ECPLL XT, HS, SOSC XTPLL, HSPLL FRC, FRCDIV FRCPLL LPRC SYSRST Delay TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST System Clock Delay -- TLOCK TOST TOST + TLOCK TFRC TFRC + TLOCK TLPRC -- TLOCK TOST TOST + TLOCK TFRC TFRC + TLOCK TLPRC Notes 1, 2, 3 1, 2, 3, 5 1, 2, 3, 4 1, 2, 3, 4, 5 1, 2, 3, 6, 7 1, 2, 3, 5, 6 1, 2, 3, 6 2, 3 2, 3, 5 2, 3, 4 2, 3, 4, 5 2, 3, 6, 7 2, 3, 5, 6 2, 3, 6 BOR Any Clock TRST -- 3 MCLR WDT Any Clock TRST -- 3 Software Any clock TRST -- 3 Illegal Opcode Any Clock TRST -- 3 Uninitialized W Any Clock TRST -- 3 Trap Conflict Any Clock TRST -- 3 Note 1: TPOR = Power-on Reset delay (10 s nominal). 2: TSTARTUP = TVREG (10 s nominal when VREGS = 1 and when VREGS = 0; depends upon WUTSEL<1:0> bits setting). 3: TRST = Internal State Reset time (32 s nominal). 4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: TLOCK = PLL lock time. 6: TFRC and TLPRC = RC Oscillator start-up times. 7: If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid. It switches to the primary oscillator after its respective clock delay. 6.3.1 POR AND LONG OSCILLATOR START-UP TIMES 6.3.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: * The oscillator circuit has not begun to oscillate. * The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). * The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR). 2010 Microchip Technology Inc. DS39969B-page 91 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 92 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 8. "Interrupts" (DS39707). The information in this data sheet supersedes the information in the FRM. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. The ALTIVT (INTCON2<15>) control bit provides access to the AIVT. If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU. It has the following features: Up to 8 processor exceptions and software traps Seven user-selectable priority levels Interrupt Vector Table (IVT) with up to 118 vectors Unique vector for each interrupt or exception source * Fixed priority within a specified user priority level * Alternate Interrupt Vector Table (AIVT) for debug support * Fixed interrupt entry and return latencies * * * * 7.2 Reset Sequence 7.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with Vector 0 will take priority over interrupts at any other vector address. PIC24FJ256DA210 family devices implement non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2. A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24F devices clear their registers in response to a Reset, which forces the PC to zero. The microcontroller then begins program execution at location, 000000h. The user programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. 2010 Microchip Technology Inc. DS39969B-page 93 PIC24FJ256DA210 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 Start of Code 000000h 000002h 000004h 000014h Decreasing Natural Order Priority 00007Ch 00007Eh 000080h Interrupt Vector Table (IVT)(1) 0000FCh 0000FEh 000100h 000102h 000114h 00017Ch 00017Eh 000180h Alternate Interrupt Vector Table (AIVT)(1) 0001FEh 000200h Note 1: See Table 7-2 for the interrupt vector list. TABLE 7-1: TRAP VECTOR DETAILS IVT Address 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h AIVT Address 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 000112h Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved Trap Source Vector Number 0 1 2 3 4 5 6 7 DS39969B-page 94 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Vector Number 13 18 67 77 0 20 29 53 54 100 17 16 50 49 85 84 1 5 37 38 39 40 22 23 93 19 72 2 6 25 26 41 42 43 44 92 45 62 9 10 32 33 90 91 IVT Address 00002Eh 000038h 00009Ah 0000AEh 000014h 00003Ch 00004Eh 00007Eh 000080h 0000DCh 000036h 000034h 000078h 000076h 0000BEh 0000BCh 000016h 00001Eh 00005Eh 000060h 000062h 000064h 000040h 000042h 0000CEh 00003Ah 0000A4h 000018h 000020h 000046h 000048h 000066h 000068h 00006Ah 00006Ch 0000CCh 00006Eh 000090h 000026h 000028h 000054h 000056h 0000C8h 0000CAh AIVT Address 00012Eh 000138h 00019Ah 0001AEh 000114h 00013Ch 00014Eh 00017Eh 000180h 0001DCh 000136h 000134h 000178h 000176h 0001BEh 0001BCh 000116h 00011Eh 00015Eh 000160h 000162h 000164h 000140h 000142h 0001CEh 00013Ah 0001A4h 000118h 000120h 000146h 000148h 000166h 000168h 00016Ah 00016Ch 0001CCh 00016Eh 000190h 000126h 000128h 000154h 000156h 0001C8h 0001CAh Interrupt Bit Locations Flag IFS0<13> IFS1<2> IFS4<3> IFS4<13> IFS0<0> IFS1<4> IFS1<13> IFS3<5> IFS3<6> IFS6<4> IFS1<1> IFS1<0> IFS3<2> IFS3<1> IFS5<5> IFS5<4> IFS0<1> IFS0<5> IFS2<5> IFS2<6> IFS2<7> IFS2<8> IFS1<6> IFS1<7> IFS5<13> IFS1<3> IFS4<8> IFS0<2> IFS0<6> IFS1<9> IFS1<10> IFS2<9> IFS2<10> IFS2<11> IFS2<12> IFS5<12> IFS2<13> IFS3<14> IFS0<9> IFS0<10> IFS2<0> IFS2<1> IFS5<10> IFS5<11> Enable IEC0<13> IEC1<2> IEC4<3> IEC4<13> IEC0<0> IEC1<4> IEC1<13> IEC3<5> IEC3<6> IEC6<4> IEC1<1> IEC1<0> IEC3<2> IEC3<1> IEC5<5> IEC5<4> IEC0<1> IEC0<5> IEC2<5> IEC2<6> IEC2<7> IEC2<8> IEC1<6> IEC1<7> IEC5<13> IEC1<3> IEC4<8> IEC0<2> IEC0<6> IEC1<9> IEC1<10> IEC2<9> IEC2<10> IEC2<11> IEC2<12> IEC5<12> IEC2<13> IEC3<14> IEC0<9> IEC0<10> IEC2<0> IEC2<1> IEC5<10> IEC5<11> Priority IPC3<6:4> IPC4<10:8> IPC16<14:12> IPC19<6:4> IPC0<2:0> IPC5<2:0> IPC7<6:4> IPC13<6:4> IPC13<10:8> IPC25<2:0> IPC4<6:4> IPC4<2:0> IPC12<10:8> IPC12<6:4> IPC21<6:4> IPC21<2:0> IPC0<6:4> IPC1<6:4> IPC9<6:4> IPC9<10:8> IPC9<14:12> IPC10<2:0> IPC5<10:8> IPC5<14:12> IPC23<6:4> IPC4<14:12> IPC18<2:0> IPC0<10:8> IPC1<10:8> IPC6<6:4> IPC6<10:8> IPC10<6:4> IPC10<10:8> IPC10<14:12> IPC11<2:0> IPC23<2:0> IPC11<6:4> IPC15<10:8> IPC2<6:4> IPC2<10:8> IPC8<2:0> IPC8<6:4> IPC22<10:8> IPC22<14:12> Interrupt Source ADC1 Conversion Done Comparator Event CRC Generator CTMU Event External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 Graphics Controller I2C1 Master Event I2C1 Slave Event I2C2 Master Event I2C2 Slave Event I2C3 Master Event I2C3 Slave Event Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 Input Capture 8 Input Capture 9 Input Change Notification (ICN) Low-Voltage Detect (LVD) Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Output Compare 6 Output Compare 7 Output Compare 8 Output Compare 9 Enhanced Parallel Master Port (EPMP)(1) Real-Time Clock and Calendar (RTCC) SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06). 2010 Microchip Technology Inc. DS39969B-page 95 PIC24FJ256DA210 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Vector Number 3 7 8 27 28 65 11 12 66 30 31 81 82 83 87 88 89 86 IVT Address 00001Ah 000022h 000024h 00004Ah 00004Ch 000096h 00002Ah 00002Ch 000098h 000050h 000052h 0000B6h 0000B8h 0000BAh 0000C2h 0000C4h 0000C6h 0000C0h AIVT Address 00011Ah 000122h 000124h 00014Ah 00014Ch 000196h 00012Ah 00012Ch 000198h 000150h 000152h 0001B6h 0001B8h 0001BAh 0001C2h 0001C4h 0001C6h 0001C0h Interrupt Bit Locations Flag IFS0<3> IFS0<7> IFS0<8> IFS1<11> IFS1<12> IFS4<1> IFS0<11> IFS0<12> IFS4<2> IFS1<14> IFS1<15> IFS5<1> IFS5<2> IFS5<3> IFS5<7> IFS5<8> IFS5<9> IFS5<6> Enable IEC0<3> IEC0<7> IEC0<8> IEC1<11> IEC1<12> IEC4<1> IEC0<11> IEC0<12> IEC4<2> IEC1<14> IEC1<15> IEC5<1> IEC5<2> IEC5<3> IEC5<7> IEC5<8> IEC5<9> IEC5<6> Priority IPC0<14:12> IPC1<14:12> IPC2<2:0> IPC6<14:12> IPC7<2:0> IPC16<6:4> IPC2<14:12> IPC3<2:0> IPC16<10:8> IPC7<10:8> IPC7<14:12> IPC20<6:4> IPC20<10:8> IPC20<14:12> IPC21<14:12> IPC22<2:0> IPC22<6:4> IPC21<10:8> Interrupt Source Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter UART3 Error UART3 Receiver UART3 Transmitter UART4 Error UART4 Receiver UART4 Transmitter USB Interrupt Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06). 7.3 Interrupt Control and Status Registers The PIC24FJ256DA210 family of devices implements a total of 40 registers for the interrupt controller: INTCON1 INTCON2 IFS0 through IFS6 IEC0 through IEC6 IPC0 through IPC25 (except IPC14, IPC17 and IPC24) * INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table (AIVT). The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or an external signal and is cleared via software. The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. * * * * * The IPCx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. The INTTREG register contains the associated interrupt vector number and the new CPU interrupt priority level, which are latched into the Vector Number (VECNUM<6:0>) and the Interrupt Level (ILR<3:0>) bit fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the order of their vector numbers, as shown in Table 7-2. For example, the INT0 (External Interrupt 0) is shown as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0<0>, the INT0IE enable bit in IEC0<0> and the INT0IP<2:0> priority bits in the first position of IPC0 (IPC0<2:0>). Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. The ALU STATUS register (SR) contains the IPL<2:0> bits (SR<7:5>). These indicate the current CPU interrupt priority level. The user can change the current CPU priority level by writing to the IPL bits. DS39969B-page 96 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY The CORCON register contains the IPL3 bit, which, together with IPL<2:0>, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. The interrupt controller has the Interrupt Controller Test register, INTTREG, which displays the status of the interrupt controller. When an interrupt request occurs, it's associated vector number and the new interrupt priority level are latched into INTTREG. This information can be used to determine a specific interrupt source if a generic ISR is used for multiple vectors (such as when ISR remapping is used in bootloader applications) or to check if another interrupt is pending while in an ISR. All interrupt registers are described in Register 7-1 through Register 7-40 in the succeeding pages. REGISTER 7-1: U-0 -- bit 15 R/W-0, HSC IPL2(2,3) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 7-5 SR: ALU STATUS REGISTER (IN CPU) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC DC(1) bit 8 R/W-0, HSC R/W-0, HSC IPL1(2,3) IPL0(2,3) R-0, HSC RA(1) R/W-0, HSC N(1) R/W-0, HSC OV(1) R/W-0, HSC R/W-0, HSC Z(1) C(1) bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15); user interrupts are disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) See Register 3-1 for the description of the remaining bits (bit 8, 4, 3, 2, 1 and 0) that are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. Note 1: 2: 3: 2010 Microchip Technology Inc. DS39969B-page 97 PIC24FJ256DA210 FAMILY REGISTER 7-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 r = Reserved bit W = Writable bit `1' = Bit is set C = Clearable bit `0' = Bit is cleared U-0 -- U-0 -- U-0 -- R/C-0, HSC IPL3(1) r-1 r U-0 -- U-0 -- bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown U-0 -- CORCON: CPU CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U = Unimplemented bit, read as `0' Unimplemented: Read as `0' IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Reserved: Read as `1' Unimplemented: Read as `0' The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level; see Register 3-2 for bit description. bit 2 bit 1-0 Note 1: DS39969B-page 98 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-3: R/W-0 NSTDIS bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0, HS MATHERR R/W-0, HS ADDRERR R/W-0, HS STKERR R/W-0, HS OSCFAIL U-0 -- bit 0 INTCON1: INTERRUPT CONTROL REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled Unimplemented: Read as `0' MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as `0' bit 14-5 bit 4 bit 3 bit 2 bit 1 bit 0 2010 Microchip Technology Inc. DS39969B-page 99 PIC24FJ256DA210 FAMILY REGISTER 7-4: R/W-0 ALTIVT bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 INT4EP R/W-0 INT3EP R/W-0 INT2EP R/W-0 INT1EP INTCON2: INTERRUPT CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 INT0EP bit 0 DISI R-0, HSC ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) vector table DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active Unimplemented: Read as `0' INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 14 bit 13-5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39969B-page 100 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-5: U-0 -- bit 15 R/W-0, HS T2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HS OC2IF R/W-0, HS IC2IF U-0 -- R/W-0, HS T1IF R/W-0, HS OC1IF R/W-0, HS IC1IF IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 -- R/W-0, HS AD1IF R/W-0, HS U1TXIF R/W-0, HS U1RXIF R/W-0, HS SPI1IF R/W-0, HS SPF1IF R/W-0, HS T3IF bit 8 R/W-0, HS INT0IF bit 0 Unimplemented: Read as `0' AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 2010 Microchip Technology Inc. DS39969B-page 101 PIC24FJ256DA210 FAMILY REGISTER 7-5: bit 1 IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 REGISTER 7-6: R/W-0, HS U2TXIF bit 15 R/W-0, HS IC8IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15 IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS INT2IF R/W-0, HS T5IF R/W-0, HS T4IF R/W-0, HS OC4IF R/W-0, HS OC3IF U-0 -- bit 8 U2RXIF R/W-0, HS R/W-0, HS IC7IF U-0 -- R/W-0, HS INT1IF R/W-0, HS CNIF R/W-0, HS CMIF R/W-0, HS MI2C1IF R/W-0, HS SI2C1IF bit 0 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 DS39969B-page 102 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-6: bit 5 bit 4 IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) Unimplemented: Read as `0' INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 bit 2 bit 1 bit 0 REGISTER 7-7: U-0 -- bit 15 R/W-0, HS IC5IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 -- R/W-0, HS PMPIF(1) R/W-0, HS OC8IF R/W-0, HS OC7IF R/W-0, HS OC6IF R/W-0, HS OC5IF R/W-0, HS IC6IF bit 8 R/W-0, HS IC4IF R/W-0, HS IC3IF U-0 -- U-0 -- U-0 -- R/W-0, HS SPI2IF R/W-0, HS SPF2IF bit 0 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' PMPIF: Parallel Master Port Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC8IF: Output Compare Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Not available in PIC24FJXXXDAX06 devices. bit 12 bit 11 bit 10 bit 9 Note 1: 2010 Microchip Technology Inc. DS39969B-page 103 PIC24FJ256DA210 FAMILY REGISTER 7-7: bit 8 IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Not available in PIC24FJXXXDAX06 devices. bit 7 bit 6 bit 5 bit 4-2 bit 1 bit 0 Note 1: DS39969B-page 104 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-8: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HS INT4IF R/W-0, HS INT3IF U-0 -- U-0 -- R/W-0, HS MI2C2IF R/W-0, HS SI2C2IF U-0 -- bit 0 IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 RTCIF R/W-0, HS Unimplemented: Read as `0' RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 13-7 bit 6 bit 5 bit 4-3 bit 2 bit 1 bit 0 2010 Microchip Technology Inc. DS39969B-page 105 PIC24FJ256DA210 FAMILY REGISTER 7-9: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0, HS CRCIF R/W-0, HS U2ERIF R/W-0, HS U1ERIF U-0 -- bit 0 IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 -- R/W-0, HS CTMUIF U-0 -- U-0 -- U-0 -- U-0 -- R/W-0, HS LVDIF bit 8 Unimplemented: Read as `0' CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' LVDIF: Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 12-9 bit 8 bit 7-4 bit 3 bit 2 bit 1 bit 0 DS39969B-page 106 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-10: U-0 -- bit 15 R/W-0, HS U4ERIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HS USB1IF R/W-0, HS MI2C3IF R/W-0, HS SI2C3IF R/W-0, HS U3TXIF R/W-0, HS U3RXIF R/W-0, HS U3ERIF U-0 -- bit 0 IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 -- R/W-0, HS IC9IF R/W-0, HS OC9IF R/W-0, HS SPI3IF R/W-0, HS SPF3IF R/W-0, HS U4TXIF R/W-0, HS U4RXIF bit 8 Unimplemented: Read as `0' IC9IF: Input Capture Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC9IF: Output Compare Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI3IF: SPI3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF3IF: SPI3 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4TXIF: UART4 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4RXIF: UART4 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4ERIF: UART4 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred USB1IF: USB1 (USB OTG) Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C3IF: Master I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C3IF: Slave I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 2010 Microchip Technology Inc. DS39969B-page 107 PIC24FJ256DA210 FAMILY REGISTER 7-10: bit 1 IFS5: INTERRUPT FLAG STATUS REGISTER 5 (CONTINUED) U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 0 REGISTER 7-11: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4 IFS6: INTERRUPT FLAG STATUS REGISTER 6 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R/W-0, HS GFX1IF U-0 -- U-0 -- U-0 -- U-0 -- bit 0 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' GFX1IF: Graphics 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' bit 3-0 DS39969B-page 108 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-12: U-0 -- bit 15 R/W-0 T2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 OC2IE R/W-0 IC2IE U-0 -- R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 -- R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 INT0IE bit 0 Unimplemented: Read as `0' AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 2010 Microchip Technology Inc. DS39969B-page 109 PIC24FJ256DA210 FAMILY REGISTER 7-12: bit 1 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 REGISTER 7-13: R/W-0 U2TXIE bit 15 R/W-0 IC8IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 INT2IE(1) R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE U-0 -- bit 8 R/W-0 U2RXIE R/W-0 IC7IE U-0 -- R/W-0 INT1IE(1) R/W-0 CNIE R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 Note 1: DS39969B-page 110 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-13: bit 6 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 111 PIC24FJ256DA210 FAMILY REGISTER 7-14: U-0 -- bit 15 R/W-0 IC5IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 IC4IE R/W-0 IC3IE U-0 -- U-0 -- U-0 -- R/W-0 SPI2IE IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 -- R/W-0 PMPIE (1) R/W-0 OC8IE R/W-0 OC7IE R/W-0 OC6IE R/W-0 OC5IE R/W-0 IC6IE bit 8 R/W-0 SPF2IE bit 0 Unimplemented: Read as `0' PMPIE: Parallel Master Port Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC8IE: Output Compare Channel 8 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Not available in 64-pin devices (PIC24FJXXXDAX06). bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 bit 1 bit 0 Note 1: DS39969B-page 112 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-15: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 INT4IE(1) R/W-0 INT3IE(1) U-0 -- U-0 -- R/W-0 MI2C2IE R/W-0 SI2C2IE U-0 -- bit 0 IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 RTCIE Unimplemented: Read as `0' RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' INT4IE: External Interrupt 4 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT3IE: External Interrupt 3 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 13-7 bit 6 bit 5 bit 4-3 bit 2 bit 1 bit 0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 113 PIC24FJ256DA210 FAMILY REGISTER 7-16: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 CRCIE R/W-0 U2ERIE R/W-0 U1ERIE U-0 -- bit 0 IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 -- R/W-0 CTMUIE U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 LVDIE bit 8 Unimplemented: Read as `0' CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' bit 12-9 bit 8 bit 7-4 bit 3 bit 2 bit 1 bit 0 DS39969B-page 114 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-17: U-0 -- bit 15 R/W-0 U4ERIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 USB1IE R/W-0 MI2C3IE R/W-0 SI2C3IE R/W-0 U3TXIE R/W-0 U3RXIE R/W-0 U3ERIE U-0 -- bit 0 IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 -- R/W-0 IC9IE R/W-0 OC9IE R/W-0 SPI3IE R/W-0 SPF3IE R/W-0 U4TXIE R/W-0 U4RXIE bit 8 Unimplemented: Read as `0' IC9IE: Input Capture Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC9IE: Output Compare Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI3IE: SPI3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF3IE: SPI3 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4TXIE: UART4 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4RXIE: UART4 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4ERIE: UART4 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled USB1IE: USB1 (USB OTG) Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C3IE: Master I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C3IE: Slave I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3TXIE: UART3 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3RXIE: UART3 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 2010 Microchip Technology Inc. DS39969B-page 115 PIC24FJ256DA210 FAMILY REGISTER 7-17: bit 1 IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 (CONTINUED) U3ERIE: UART3 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' bit 0 REGISTER 7-18: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4 IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R/W-0 GFX1IE U-0 -- U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' GFX1IE: Graphics 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as `0' bit 3-0 DS39969B-page 116 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-19: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC1IP2 R/W-0 IC1IP1 R/W-0 IC1IP0 U-0 -- R/W-1 INT0IP2 R/W-0 INT0IP1 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-0 T1IP1 R/W-0 T1IP0 U-0 -- R/W-1 OC1IP2 R/W-0 OC1IP1 R/W-0 OC1IP0 bit 8 R/W-0 INT0IP0 bit 0 R/W-1 T1IP2 Unimplemented: Read as `0' T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. DS39969B-page 117 PIC24FJ256DA210 FAMILY REGISTER 7-20: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC2IP2 R/W-0 IC2IP1 R/W-0 IC2IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-0 T2IP1 R/W-0 T2IP0 U-0 -- R/W-1 OC2IP2 R/W-0 OC2IP1 R/W-0 OC2IP0 bit 8 R/W-1 T2IP2 Unimplemented: Read as `0' T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39969B-page 118 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-21: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SPF1IP2 R/W-0 SPF1IP1 R/W-0 SPF1IP0 U-0 -- R/W-1 T3IP2 R/W-0 T3IP1 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-0 U1RXIP1 R/W-0 U1RXIP0 U-0 -- R/W-1 SPI1IP2 R/W-0 SPI1IP1 R/W-0 SPI1IP0 bit 8 R/W-0 T3IP0 bit 0 R/W-1 U1RXIP2 Unimplemented: Read as `0' U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. DS39969B-page 119 PIC24FJ256DA210 FAMILY REGISTER 7-22: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 AD1IP2 R/W-0 AD1IP1 R/W-0 AD1IP0 U-0 -- R/W-1 U1TXIP2 R/W-0 U1TXIP1 IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 U1TXIP0 bit 0 Unimplemented: Read as `0' AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 120 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-23: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 MI2C1IP2 R/W-0 MI2C1IP1 R/W-0 MI2C1IP0 U-0 -- R/W-1 SI2C1IP2 R/W-0 SI2C1IP1 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-0 CNIP1 R/W-0 CNIP0 U-0 -- R/W-1 CMIP2 R/W-0 CMIP1 R/W-0 CMIP0 bit 8 R/W-0 SI2C1IP0 bit 0 R/W-1 CNIP2 Unimplemented: Read as `0' CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. DS39969B-page 121 PIC24FJ256DA210 FAMILY REGISTER 7-24: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 INT1IP2 R/W-0 INT1IP1 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 R/W-0 IC8IP1 R/W-0 IC8IP0 U-0 -- R/W-1 IC7IP2 R/W-0 IC7IP1 R/W-0 IC7IP0 bit 8 R/W-0 INT1IP0 bit 0 R/W-1 IC8IP2 Unimplemented: Read as `0' IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-3 bit 2-0 Unimplemented: Read as `0' INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 122 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-25: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 OC3IP2 R/W-0 OC3IP1 R/W-0 OC3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-0 T4IP1 R/W-0 T4IP0 U-0 -- R/W-1 OC4IP2 R/W-0 OC4IP1 R/W-0 OC4IP0 bit 8 R/W-1 T4IP2 Unimplemented: Read as `0' T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' 2010 Microchip Technology Inc. DS39969B-page 123 PIC24FJ256DA210 FAMILY REGISTER 7-26: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT2IP2 R/W-0 INT2IP1 R/W-0 INT2IP0 U-0 -- R/W-1 T5IP2 R/W-0 T5IP1 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-0 U2TXIP1 R/W-0 U2TXIP0 U-0 -- R/W-1 U2RXIP2 R/W-0 U2RXIP1 R/W-0 U2RXIP0 bit 8 R/W-0 T5IP0 bit 0 R/W-1 U2TXIP2 Unimplemented: Read as `0' U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 124 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-27: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SPI2IP2 R/W-0 SPI2IP1 R/W-0 SPI2IP0 U-0 -- R/W-1 SPF2IP2 R/W-0 SPF2IP1 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 SPF2IP0 bit 0 Unimplemented: Read as `0' SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. DS39969B-page 125 PIC24FJ256DA210 FAMILY REGISTER 7-28: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC3IP2 R/W-0 IC3IP1 R/W-0 IC3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 R/W-0 IC5IP1 R/W-0 IC5IP0 U-0 -- R/W-1 IC4IP2 R/W-0 IC4IP1 R/W-0 IC4IP0 bit 8 R/W-1 IC5IP2 Unimplemented: Read as `0' IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39969B-page 126 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-29: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 OC5IP2 R/W-0 OC5IP1 R/W-0 OC5IP0 U-0 -- R/W-1 IC6IP2 R/W-0 IC6IP1 IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 R/W-0 OC7IP1 R/W-0 OC7IP0 U-0 -- R/W-1 OC6IP2 R/W-0 OC6IP1 R/W-0 OC6IP0 bit 8 R/W-0 IC6IP0 bit 0 R/W-1 OC7IP2 Unimplemented: Read as `0' OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. DS39969B-page 127 PIC24FJ256DA210 FAMILY REGISTER 7-30: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 PMPIP2(1) R/W-0 PMPIP1(1) R/W-0 PMPIP0(1) U-0 -- R/W-1 OC8IP2 R/W-0 OC8IP1 IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 OC8IP0 bit 0 Unimplemented: Read as `0' PMPIP<2:0>: Parallel Master Port Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Not available in 64-pin devices (PIC24FJXXXDAX06). DS39969B-page 128 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-31: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 SI2C2IP2 R/W-0 SI2C2IP1 R/W-0 SI2C2IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 MI2C2IP2 R/W-0 MI2C2IP1 R/W-0 MI2C2IP0 bit 8 Unimplemented: Read as `0' MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' 2010 Microchip Technology Inc. DS39969B-page 129 PIC24FJ256DA210 FAMILY REGISTER 7-32: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INT3IP2 R/W-0 INT3IP1 R/W-0 INT3IP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 INT4IP2 R/W-0 INT4IP1 R/W-0 INT4IP0 bit 8 Unimplemented: Read as `0' INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39969B-page 130 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-33: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 RTCIP2 R/W-0 RTCIP1 R/W-0 RTCIP0 bit 8 Unimplemented: Read as `0' RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as `0' 2010 Microchip Technology Inc. DS39969B-page 131 PIC24FJ256DA210 FAMILY REGISTER 7-34: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U1ERIP2 R/W-0 U1ERIP1 R/W-0 U1ERIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 R/W-0 CRCIP1 R/W-0 CRCIP0 U-0 -- R/W-1 U2ERIP2 R/W-0 U2ERIP1 R/W-0 U2ERIP0 bit 8 R/W-1 CRCIP2 Unimplemented: Read as `0' CRCIP<2:0>: CRC Generator Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' U2ERIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39969B-page 132 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-35: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 LVDIP2 R/W-0 LVDIP1 IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 LVDIP0 bit 0 Unimplemented: Read as `0' LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled REGISTER 7-36: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 CTMUIP2 R/W-0 CTMUIP1 R/W-0 CTMUIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' 2010 Microchip Technology Inc. DS39969B-page 133 PIC24FJ256DA210 FAMILY REGISTER 7-37: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U3ERIP2 R/W-0 U3ERIP1 R/W-0 U3ERIP0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 R/W-0 U3TXIP1 R/W-0 U3TXIP0 U-0 -- R/W-1 U3RXIP2 R/W-0 U3RXIP1 R/W-0 U3RXIP0 bit 8 R/W-1 U3TXIP2 Unimplemented: Read as `0' U3TXIP<2:0>: UART3 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' U3RXIP<2:0>: UART3 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' U3ERIP<2:0>: UART3 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39969B-page 134 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-38: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 MI2C3IP2 R/W-0 MI2C3IP1 R/W-0 MI2C3IP0 U-0 -- R/W-1 SI2C3IP2 R/W-0 SI2C3IP1 IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 R/W-0 U4ERIP1 R/W-0 U4ERIP0 U-0 -- R/W-1 USB1IP2 R/W-0 USB1IP1 R/W-0 USB1IP0 bit 8 R/W-0 SI2C3IP0 bit 0 R/W-1 U4ERIP2 Unimplemented: Read as `0' U4ERIP<2:0>: UART4 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' USB1IP<2:0>: USB1 (USB OTG) Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' MI2C3IP<2:0>: Master I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' SI2C3IP<2:0>: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. DS39969B-page 135 PIC24FJ256DA210 FAMILY REGISTER 7-39: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 U4TXIP2 R/W-0 U4TXIP1 R/W-0 U4TXIP0 U-0 -- R/W-1 U4RXIP2 R/W-0 U4RXIP1 IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 R/W-0 SPI3IP1 R/W-0 SPI3IP0 U-0 -- R/W-1 SPF3IP2 R/W-0 SPF3IP1 R/W-0 SPF3IP0 bit 8 R/W-0 U4RXIP0 bit 0 R/W-1 SPI3IP2 Unimplemented: Read as `0' SPI3IP<2:0>: SPI3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 Unimplemented: Read as `0' SPF3IP<2:0>: SPI3 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 bit 6-4 Unimplemented: Read as `0' U4TXIP<2:0>: UART4 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' U4RXIP<2:0>: UART4 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 136 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-40: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 IC9IP2 R/W-0 IC9IP1 R/W-0 IC9IP0 U-0 -- R/W-1 OC9IP2 R/W-0 OC9IP1 IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 OC9IP0 bit 0 Unimplemented: Read as `0' IC9IP<2:0>: Input Capture Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 Unimplemented: Read as `0' OC9IP<2:0>: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2010 Microchip Technology Inc. DS39969B-page 137 PIC24FJ256DA210 FAMILY REGISTER 7-41: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 GFX1IP2 R/W-0 GFX1IP1 IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 GFX1IP0 bit 0 Unimplemented: Read as `0' GFX1IP<2:0>: Graphics 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39969B-page 138 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 7-42: R-0, HSC CPUIRQ bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0, HSC VECNUM6 R-0, HSC VECNUM5 R-0, HSC VECNUM4 R-0, HSC VECNUM3 R-0, HSC VECNUM2 R-0, HSC VECNUM1 INTTREG: INTERRUPT CONTROLLER TEST REGISTER U-0 -- R/W-0 VHOLD U-0 -- R-0, HSC ILR3 R-0, HSC ILR2 R-0, HSC ILR1 R-0, HSC ILR0 bit 8 R-0, HSC VECNUM0 bit 0 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens when the CPU priority is higher than the interrupt priority 0 = No interrupt request is unacknowledged Unimplemented: Read as `0' VHOLD: Vector Number Capture Configuration bit 1 = The VECNUM bits contain the value of the highest priority pending interrupt 0 = The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) Unimplemented: Read as `0' ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 * * * bit 14 bit 13 bit 12 bit 11-8 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 bit 6-0 Unimplemented: Read as `0' VECNUM<5:0>: Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits VHOLD = 1: The VECNUM bits indicate the vector number (from 0 to 118) of the last interrupt to occur VHOLD = 0: The VECNUM bits indicate the vector number (from 0 to 118) of the interrupt request currently being handled 2010 Microchip Technology Inc. DS39969B-page 139 PIC24FJ256DA210 FAMILY 7.4 7.4.1 1. 2. Interrupt Setup Procedures INITIALIZATION 7.4.3 TRAP SERVICE ROUTINE (TSR) To configure an interrupt source: Set the NSTDIS (INTCON1<15>) control bit if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to priority level 4. A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 7.4.4 INTERRUPT DISABLE All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value 0Eh with SRL. To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (Level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels, 1-6, for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. 3. 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 7.4.2 INTERRUPT SERVICE ROUTINE (ISR) The method that is used to declare an Interrupt Service Routine (ISR) and initialize the IVT with the correct vector address will depend on the programming language (i.e., `C' or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS39969B-page 140 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 8.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 6. "Oscillator" (DS39700). The information in this data sheet supersedes the information in the FRM. The oscillator system for PIC24FJ256DA210 family devices has the following features: * A total of four external and internal oscillator options as clock sources, providing 11 different clock modes * An on-chip PLL block to boost internal operating frequency on select internal and external oscillator sources, and to provide a precise clock source for peripherals, such as USB and graphics * Software controllable switching between various clock sources * Software controllable postscaler for selective clocking of CPU for system power savings * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown * A separate and independently configurable system clock output for synchronizing external hardware A simplified diagram of the oscillator system is shown in Figure 8-1. FIGURE 8-1: PIC24FJ256DA210 FAMILY CLOCK DIAGRAM PIC24FJ256DA210 Family Clock for Display Interface 48/96 MHz Clock for Graphics Controller Module 48 MHz USB Clock Primary Oscillator OSCO XT, HS, EC 96 MHz PLL(1) CPDIV<1:0> REFOCON<15:8> Reference Clock Generator REFO OSCI PLL and DIV PLLDIV<2:0> GCLKDIV<6:0> XTPLL, HSPLL ECPLL,FRCPLL Peripherals FRC Oscillator Postscaler 8 MHz/ 4 MHz FRCDIV CLKO Postscaler 8 MHz (nominal) CLKDIV<10:8> 1/16 LPRC Oscillator FRC LPFRC LPRC CPU 31 kHz (nominal) CLKDIV<14:12> SOSC Secondary Oscillator SOSCO SOSCI SOSCEN Enable Oscillator Clock Control Logic Fail-Safe Clock Monitor WDT Clock Source Option for Other Modules Note 1: Refer to Figure 8-2 for more information on the 96 MHz PLL block. 2010 Microchip Technology Inc. DS39969B-page 141 PIC24FJ256DA210 FAMILY 8.1 CPU Clocking Scheme 8.2 Initial Configuration on POR The system clock source can be provided by one of four sources: * Primary Oscillator (POSC) on the OSCI and OSCO pins * Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins * Fast Internal RC (FRC) Oscillator * Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal 24x PLL block, which generates the USB module clock, the Graphics module clock and a separate system clock through the 96 MHZ PLL. Refer to Section 8.5 "96 MHz PLL Block" for additional information. The internal FRC provides an 8 MHz clock source. It can optionally be reduced by the programmable clock divider to provide a range of system clock frequencies. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the primary oscillator. The oscillator source (and operating mode) that is used at a device Power-on Reset (POR) event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 27.1 "Configuration Bits" for further details). The Primary Oscillator Configuration bits, POSCMD<1:0> (Configuration Word 2<1:0>) and the Initial Oscillator Select Configuration bits, FNOSC<2:0> (Configuration Word 2<10:8>), select the oscillator source that is used at a POR. The FRC primary oscillator with postscaler (FRCDIV) is the default (unprogrammed) selection. The secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The Configuration bits allow users to choose between the various clock modes, shown in Table 8-1. 8.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS The FCKSM Configuration bits (Configuration Word 2<7:6>) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (`0'). The FSCM is enabled only when FCKSM<1:0> are both programmed (`00'). TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Source Internal Internal Internal Secondary Primary Primary Primary Primary Primary Internal Internal POSCMD<1:0> 11 11 11 11 01 00 10 01 00 11 11 FNOSC<2:0> 111 110 101 100 011 011 010 010 010 001 000 Notes 1, 2 1 1 1 -- 1 -- -- 1 1 1 Oscillator Mode Fast RC Oscillator with Postscaler (FRCDIV) FRC Oscillator/16 (500 KHz) Low-Power RC Oscillator (LPRC) Secondary (Timer1) Oscillator (SOSC) Primary Oscillator (XT) with PLL Module (XTPLL) Primary Oscillator (EC) with PLL Module (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL Module (FRCPLL) Fast RC Oscillator (FRC) Note 1: 2: OSCO pin function is determined by the OSCIOFCN Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS39969B-page 142 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 8.3 Control Registers The following five Special Function Registers control the operation of the oscillator: * * * * * OSCCON CLKDIV OSCTUN CLKDIV2 REFOCON The OSCCON register (Register 8-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. The OSCTUN register (Register 8-3) allows the user to fine tune the FRC oscillator over a range of approximately 1.5%. The CLKDIV2 register (Register 8-4) controls the clock to the display glass, with the frequency ranging from 750 kHz to 96 MHz. The REFOCON register (Register 8-5) controls the frequency of the reference clock out. REGISTER 8-1: U-0 -- bit 15 R/S-0 CLKLOCK bit 7 Legend: R = Readable bit -n = Value at POR OSCCON: OSCILLATOR CONTROL REGISTER U-0 -- R/W-x(1) NOSC2 R/W-x(1) NOSC1 R/W-x(1) NOSC0 bit 8 COSC1 COSC0 R-x, HSC(1) R-x, HSC(1) R-x, HSC(1) COSC2 R/W-0 IOLOCK(2) R-0, HSC(3) LOCK U-0 -- R/C-0, HS CF R/W-0 POSCEN R/W-0 SOSCEN R/W-0 OSWEN bit 0 C = Clearable bit W = Writable bit `1' = Bit is set S = Settable bit `0' = Bit is cleared HSC = Hardware Settable/Clearable bit x = Bit is unknown U = Unimplemented bit, read as `0' HS = Hardware Settable bit bit 15 bit 14-12 Unimplemented: Read as `0' COSC<2:0>: Current Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Fast RC/16 Oscillator 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Unimplemented: Read as `0' Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is `1', once the IOLOCK bit is set, it cannot be cleared. Also resets to `0' during any valid clock switch or whenever a non PLL Clock mode is selected. bit 11 Note 1: 2: 3: 2010 Microchip Technology Inc. DS39969B-page 143 PIC24FJ256DA210 FAMILY REGISTER 8-1: bit 10-8 OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) NOSC<2:0>: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Fast RC/16 Oscillator 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled Unimplemented: Read as `0' CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary Oscillator continues to operate during Sleep mode 0 = Primary Oscillator is disabled during Sleep mode SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable the Secondary Oscillator 0 = Disable the Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to the clock source specified by the NOSC<2:0> bits 0 = Oscillator switch is complete Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is `1', once the IOLOCK bit is set, it cannot be cleared. Also resets to `0' during any valid clock switch or whenever a non PLL Clock mode is selected. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: DS39969B-page 144 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 8-2: R/W-0 ROI bit 15 R/W-0 CPDIV1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CPDIV0 R/W-0 PLLEN R/W-0 G1CLKSEL U-0 -- U-0 -- U-0 -- U-0 -- bit 0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 DOZE2 R/W-0 DOZE1 R/W-0 DOZE0 R/W-0 DOZEN (1) R/W-0 RCDIV2 R/W-0 RCDIV1 R/W-1 RCDIV0 bit 8 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit DOZE<2:0>: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 DOZEN: DOZE Enable bit(1) 1 = DOZE<2:0> bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio is set to 1:1 RCDIV<2:0>: FRC Postscaler Select bits 111 = 31.25 kHz (divide by 256) 110 = 125 kHz (divide by 64) 101 = 250 kHz (divide by 32) 100 = 500 kHz (divide by 16) 011 = 1 MHz (divide by 8) 010 = 2 MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) CPDIV<1:0>: System Clock Select bits (postscaler select from 32 MHz clock branch) 11 = 4 MHz (divide by 8)(2) 10 = 8 MHz (divide by 4)(2) 01 = 16 MHz (divide by 2) 00 = 32 MHz (divide by 1) This bit is automatically cleared when the ROI bit is set and an interrupt occurs. This setting is not allowed while the USB module is enabled. bit 14-12 bit 11 bit 10-8 bit 7-6 Note 1: 2: 2010 Microchip Technology Inc. DS39969B-page 145 PIC24FJ256DA210 FAMILY REGISTER 8-2: bit 5 CLKDIV: CLOCK DIVIDER REGISTER (CONTINUED) PLLEN: 96 MHz PLL Enable bit The 96 MHz PLL must be enabled when the USB or graphics controller module is enabled. This control bit can be overridden by the PLL96MHZ (Configuration Word 2 <11>) Configuration bit. 1 = Enable the 96 MHz PLL for USB, graphics controller or HSPLL/ECPLL/FRCPLL operation 0 = Disable the 96 MHz PLL G1CLKSEL: Display Controller Module Clock Select bit 1 = Use the 96 MHz clock as a graphics controller module clock 0 = Use the 48 MHz clock as a graphics controller module clock Unimplemented: Read as `0' This bit is automatically cleared when the ROI bit is set and an interrupt occurs. This setting is not allowed while the USB module is enabled. bit 4 bit 3-0 Note 1: 2: REGISTER 8-3: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- R/W-0 TUN5(1) R/W-0 TUN4(1) R/W-0 TUN3(1) R/W-0 TUN2(1) R/W-0 TUN1(1) R/W-0 TUN0(1) bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 = * * * 000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 = * * * 100001 = 100000 = Minimum frequency deviation Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. Note 1: DS39969B-page 146 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 8-4: R/W-0 GCLKDIV6 bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at all Resets bit 15-9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- (1) CLKDIV2: CLOCK DIVIDER REGISTER 2 R/W-0 R/W-0 (1) R/W-0 (1) R/W-0 (1) R/W-0 (1) R/W-0 (1) U-0 (1) GCLKDIV5 GCLKDIV4 GCLKDIV3 GCLKDIV2 GCLKDIV1 GCLKDIV0 -- bit 8 U-0 -- bit 0 GCLKDIV<6:0>: Display Module Interface Clock Divider Selection bits(1) (Values are based on a 96 MHz clock source set by G1CLKSEL (CLKDIV<4>) = 1. When the 48 MHz clock source is selected, G1CLKSEL (CLKDIV<4>) = 0; all values are divided by 2.)(1) 1111111 = (127) 1.50 MHz (divide by 64) 1111110 = (126) 1.52 MHz (divide by 63) * * * 1100001 = (97) 2.82 MHz (divide by 34) 1100000 = (96) 2.91 MHz (divide by 33); from here, increment the divisor by 1.00 1011111 = (95) 2.95 MHz (divide by 32.50) * * * 1000000 = (65) 5.49 MHz (divide by 17.50) 1000000 = (64) 5.65 MHz (divide by 17.00); from here, increment the divisor by 0.50 0111111 = (63) 5.73 MHz (divide by 16.75) * * * 0000011 = (3) 54.86 MHz (divide by 1.75) 0000010 = (2) 64.00 MHz (divide by 1.5) 0000001 = (1) 76.80 MHz (divide by 1.25); from here, increment the divisor by 0.25 0000000 = (0) 96.00 MHz (divide by 1) Unimplemented: Read as `0' These bits take effect only when the 96 MHz PLL is enabled. bit 8-0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 147 PIC24FJ256DA210 FAMILY 8.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: The Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMDx Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and CF (OSCCON<3>) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bit values are transferred to the COSCx bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or SOSC (if SOSCEN remains set). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL modes are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 2. 3. 8.4.1 ENABLING CLOCK SWITCHING 4. To enable clock switching, the FCKSM1 Configuration bit in CW2 must be programmed to `0'. (Refer to Section 27.1 "Configuration Bits" for further details.) If the FCKSM1 Configuration bit is unprogrammed (`1'), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSCx (OSCCON<10:8>) control bits do not control the clock selection when clock switching is disabled. However, the COSCx (OSCCON<14:12>) control bits will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN (OSCCON<0>) control bit has no effect when clock switching is disabled; It is held at `0' at all times. 5. 6. 8.4.2 OSCILLATOR SWITCHING SEQUENCE At a minimum, performing a clock switch requires this basic sequence: 1. If desired, read the COSCx (OSCCON<14:12>) control bits to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx (OSCCON<10:8>) control bits for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch. 2. 3. 4. 5. DS39969B-page 148 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY A recommended code sequence for a clock switch includes the following: 1. 2. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON<7:0> in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock-sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is `0'. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of failure. 8.5 96 MHz PLL Block The 96 MHz PLL block is implemented to generate the stable 48 MHz clock required for full-speed USB operation, a programmable clock output for the graphics controller module and the system clock from the same oscillator source. The 96 MHz PLL block is shown in Figure 8-2. The 96 MHz PLL block requires a 4 MHz input signal; it uses this to generate a 96 MHz signal from a fixed, 24x PLL. This is, in turn, divided into three branches. The first branch generates the USB clock, the second branch generates the system clock and the third branch generates the graphics clock. The 96 MHz PLL block can be enabled and disabled using the PLL96MHZ Configuration bit (Configuration Word<11>) or through the PLLEN (CLKDIV<5>) control bit when the PLL96MHZ Configuration bit is not set. Note that the PLL96MHZ Configuration bit and PLLEN register bit are available only for PIC24F devices with USB and graphics controller modules. The 96 MHz PLL prescaler does not automatically sense the incoming oscillator frequency. The user must manually configure the PLL divider to generate the required 4 MHz output, using the PLLDIV<2:0> Configuration bits (Configuration Word 2<14:12> in most devices). 3. 4. 5. 6. 7. 8. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 8-1. EXAMPLE 8-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING IN ASSEMBLY ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 2010 Microchip Technology Inc. DS39969B-page 149 PIC24FJ256DA210 FAMILY FIGURE 8-2: 96 MHz PLL BLOCK USB Clock /2 96 MHz PLL FNOSC<2:0> /12 /8 /6 /5 /4 /3 /2 /1 PLLDIV<2:0> Postscaler System Clock /8 /4 /2 /1 11 10 01 00 PLL Output for System Clock 48 MHz Clock for USB Module /3 PLL Prescaler Input from POSC Input from FRC 4 MHz or 8 MHz 111 110 101 100 011 010 001 000 CPDIV<1:0> Graphics Clock /2 48 MHz Branch Graphics Clock Option 2 / 64 / 63 ... / 17.50 / 17.00 ... / 1.25 /1 4 MHz Branch 96 MHz PLL 96 MHz Branch G1CLKSEL Graphics Clock Option 1 0 1 127 126 ... 65 64 ... 1 0 . . . GCLKDIV<6:0> Postscaler Clock Output for Display Interface (DISPCLK) Clock Output for Graphics Controller Module (G1CLK) 8.5.1 SYSTEM CLOCK GENERATION The system clock is generated from the 96 MHz branch using a configurable postscaler/divider to generate a range of frequencies for the system clock multiplexer. The output of the multiplexer is further passed through a fixed divide-by-3 divider and the final output is used as the system clock. Figure 8-2 shows this logic in the system clock sub-block. Since the source is a 96 MHz signal, the possible system clock frequencies are listed in Table 8-2. The available system clock options are always the same, regardless of the setting of the PLLDIV Configuration bits. TABLE 8-2: SYSTEM CLOCK OPTIONS FOR 96 MHz PLL BLOCK MCU Clock Division (CPDIV<1:0>) None (00) 2 (01) 4 (10) 8 (11) System Clock Frequency (Instruction Rate in MIPS) 32 MHz (16) 16 MHz (8) 8 MHz (4)(1) 4 MHz (2)(1) Note 1: These options are not compatible with USB operation. They may be used whenever the PLL branch is selected and the USB module is disabled. DS39969B-page 150 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 8.5.2 USB CLOCK GENERATION In the USB-On-The-Go module in PIC24FJ256DA210 family of devices, the primary oscillator with the PLL block can be used as a valid clock source for USB operation. The FRC oscillator (implemented with 0.25% accuracy) can be combined with a PLL block, providing another option for a valid USB clock source. There is no provision to provide a separate external 48 MHz clock to the USB module. The USB module sources its clock signal from 96 MHz PLL. Due to the requirement that a 4 MHz input must be provided to generate the 96 MHz signal, the oscillator operation is limited to a range of possible values. Table 8-3 shows the valid oscillator configurations (i.e., ECPLL, HSPLL, XTPLL and FRCPLL) for USB operation. This sets the correct PLLDIV configuration for the specified oscillator frequency and the output frequency of the USB clock branch is always 48 MHz. TABLE 8-3: VALID OSCILLATOR CONFIGURATIONS FOR USB OPERATIONS Clock Mode ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL ECPLL, HSPLL, XTPLL, FRCPLL ECPLL, HSPLL, XTPLL, FRCPLL PLL Division (PLLDIV<2:0>) 12 (111) 8 (110) 6 (101) 5 (100) 4 (011) 3 (010) 2 (001) 1 (000) Input Oscillator Frequency 48 MHz 32 MHz 24 MHz 20 MHz 16 MHz 12 MHz 8 MHz 4 MHz Note: For USB devices, the use of a primary oscillator or external clock source, with a frequency above 32 MHz, does not imply that the device's system clock can be run at the same speed when the USB module is not used. The maximum system clock for all PIC24F devices is 32 MHz. 8.5.3 CONSIDERATIONS FOR USB OPERATION 8.5.4 GRAPHICS CLOCK GENERATION When using the USB On-The-Go module in PIC24FJ256DA210 family devices, users must always observe these rules in configuring the system clock: * For USB operation, the selected clock source (EC, HS or XT) must meet the USB clock tolerance requirements. * The Primary Oscillator/PLL modes are the only oscillator configurations that permit USB operation. There is no provision to provide a separate external clock source to the USB module. * While the FRCPLL Oscillator mode is used for USB applications, users must always ensure that the FRC source is configured to provide a frequency of 4 MHz or 8 MHz (RCDIV<2:0> = 001 or 000) and that the USB PLL prescaler is configured appropriately. All other oscillator modes are available; however, USB operation is not possible when these modes are selected. They may still be useful in cases where other power levels of operation are desirable and the USB module is not needed (e.g., the application is sleeping and waiting for a bus attachment). Two stable clock signals are generated for the graphics controller in the PIC24FJ256DA210 family of devices. The first clock is for the graphics controller module logic and the second clock is for the display module interface logic that generates the signals for the display glass. Figure 8-2 shows this logic in the graphics clock sub-block. Both clock signals are generated either from the Graphics Clock Option 1 (96 MHz branch) or the Graphics Clock Option 2 (48 MHz branch). Selection is set in the multiplexer using the G1CLKSEL (CLKDIV<4>) control bit. Graphics controller module logic directly uses the output of that multiplexer while the display module interface clock is further conditioned through a postscaler to generate 128 possible frequencies. The final clock output signal is selected through a multiplexer using the GCLKDIV<6:0> (CLKDIV2<15:9>) control bits. The 128 selections vary in increments of 0.25, 0.5, and 1.0. Refer to Table 8-4 for details. Note that for applications that use the graphics controller (GFX) module, the 96 MHz PLL must be enabled. 2010 Microchip Technology Inc. DS39969B-page 151 PIC24FJ256DA210 FAMILY TABLE 8-4: DISPLAY MODULE CLOCK FREQUENCY DIVISION Frequency Divisor 1 1.25 (start incrementing by 0.25) 1.5 ... 16.75 17 17.5 (start incrementing by 0.5) 18 ... 32.5 33 34 (start incrementing by 1) 35 ... 63 64 Display Module Clock Frequency 96 MHz Input (48 MHz Input) 96 MHz (48 MHz) 76.80 MHz (38.4 MHz) 64 MHz (32 MHz) ... 5.73 MHz (2.86 MHz) 5.65 MHz (2.82 MHz) 5.49 MHz (2.74 MHz) 5.33 MHz (2.66 MHz) ... 2.95 MHz (1.47 MHz) 2.91 MHz (1.45 MHz) 2.82 MHz (1.41 MHz) 2.74 MHz (1.37 MHz) ... 1.52 MHz (762 kHz) 1.50 MHz (750 kHz) The ROSSLP and ROSEL bits (REFOCON<13:12>) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSCI and OSCO, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the POSCEN bit is not also set, the oscillator on OSCI and OSCO will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. GCLKDIV<6:0> 0000000 0000001 0000010 ... 0111111 1000000 1000001 1000010 ... 1011111 1100000 1100001 1100010 ... 1111110 1111111 8.6 Reference Clock Output In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24FJ256DA210 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 8-5). Setting the ROEN bit (REFOCON<15>) makes the clock signal available on the REFO pin. The RODIV bits (REFOCON<11:8>) enable the selection of 16 different clock divider options. DS39969B-page 152 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 8-5: R/W-0 ROEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER U-0 -- R/W-0 ROSSLP R/W-0 ROSEL (1) R/W-0 RODIV3 R/W-0 RODIV2 R/W-0 RODIV1 R/W-0 RODIV0 bit 8 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled Unimplemented: Read as `0' ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep ROSEL: Reference Oscillator Source Select bit(1) 1 = Primary oscillator used as the base clock 0 = System clock used as the base clock; base clock reflects any clock switching of the device RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value Unimplemented: Read as `0' Note that the crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode. bit 14 bit 13 bit 12 bit 11-8 bit 7-0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 153 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 154 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 10. "Power-Saving Features" (DS39698). The information in this data sheet supersedes the information in the FRM. 9.2.1 SLEEP MODE Sleep mode has these features: * The system clock source is shut down. If an on-chip oscillator is used, it is turned off. * The device current consumption will be reduced to a minimum, provided that no I/O pin is sourcing current. * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode since the system clock source is disabled. * The LPRC clock will continue to run in Sleep mode if the WDT is enabled. * The WDT, if enabled, is automatically cleared prior to entering Sleep mode. * Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. Users can opt to make the voltage regulator enter standby mode on entering Sleep mode by clearing the VREGS bit (RCON<8>). This will decrease current consumption but will add a delay, TVREG, to the wake-up time. For this reason, applications that do not use the voltage regulator should set this bit. The device will wake-up from Sleep mode on any of the these events: * On any interrupt source that is individually enabled * On any form of device Reset * On a WDT time-out On wake-up from sleep, the processor will restart with the same clock source that was active when Sleep mode was entered. The PIC24FJ256DA210 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: * * * * Clock Frequency Instruction-Based Sleep and Idle modes Software Controlled Doze mode Selective Peripheral Control in Software Combinations of these methods can be used to selectively tailor an application's power consumption, while still maintaining critical application features, such as timing-sensitive communications. 9.1 Clock Frequency and Clock Switching PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 8.0 "Oscillator Configuration". 9.2 Instruction-Based Power-Saving Modes EXAMPLE 9-1: PWRSAV PWRSAV #0 #1 PWRSAV INSTRUCTION SYNTAX ; Put the device into SLEEP mode ; Put the device into IDLE mode PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 9-1. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to "wake-up". 2010 Microchip Technology Inc. DS39969B-page 155 PIC24FJ256DA210 FAMILY 9.2.2 IDLE MODE Idle mode has these features: * The CPU will stop executing instructions. * The WDT is automatically cleared. * The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 "Selective Peripheral Module Control"). * If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: * Any interrupt that is individually enabled. * Any device Reset. * A WDT time-out. On wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR. It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. 9.4 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: * The Peripheral Enable bit, generically named, "XXXEN", located in the module's main control SFR. * The Peripheral Module Disable (PMD) bit, generically named, "XXXMD", located in one of the PMD control registers. Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. This reduces power consumption, but not by as much as setting the PMD bit does. Most peripheral modules have an enable bit; exceptions include input capture, output compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, "XXXIDL". By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications. 9.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 9.3 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default. DS39969B-page 156 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 10.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 12. "I/O Ports with Peripheral Pin Select (PPS)" (DS39711). The information in this data sheet supersedes the information in the FRM. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/O and one register associated with their operation as analog input. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Output Latch register (LATx), read the latch; writes to the latch, write the latch. Reads from the port (PORTx), read the port pins; writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers, and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is regarded as a dedicated port because there is no other competing source of inputs. All of the device pins (except VDD, VSS, MCLR and OSCI/CLKI) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger (ST) inputs for improved noise immunity. 10.1 Parallel I/O (PIO) Ports A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data 1 0 1 0 Output Enable Output Multiplexers I/O PIO Module Read TRIS Output Data Data Bus WR TRIS D CK Q I/O Pin TRIS Latch D WR LAT + WR PORT CK Data Latch Q Read LAT Input Data Read PORT 2010 Microchip Technology Inc. DS39969B-page 157 PIC24FJ256DA210 FAMILY 10.1.1 I/O PORT WRITE/READ TIMING 10.2 One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. Configuring Analog Port Pins (ANSEL) 10.1.2 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either a digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. The ANSx and TRISx registers control the operation of the pins with analog function. Each port pin with analog function is associated with one of the ANS bits (see Register 10-1 through Register 10-7), which decides if the pin function should be analog or digital. Refer to Table 10-1 for detailed behavior of the pin for different ANSx and TRISx bit settings. When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). 10.2.1 ANALOG INPUT PINS AND VOLTAGE CONSIDERATIONS 10.1.3 CONFIGURING D+ AND D- PINS (RG2 AND RG3) The input buffers of the RG2 and RG3 pins are by default, tri-stated. To use these pins as input pins, the UTRDIS bit (U1CNFG2<0>) should be set which enables the input buffers on these pins. The voltage tolerance of pins used as device inputs is dependent on the pin's input function. Pins that are used as digital only inputs are able to handle DC voltages of up to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should always be avoided. Table 10-2 summarizes the input capabilities. Refer to Section 30.1 "DC Characteristics" for more details. TABLE 10-1: Pin Function Analog Input Analog Output Digital Input CONFIGURING ANALOG/DIGITAL FUNCTION OF AN I/O PIN ANSx Setting 1 1 0 TRISx Setting 1 1 1 Comments It is recommended to keep ANSx = 1. It is recommended to keep ANSx = 1. Firmware must wait at least one instruction cycle after configuring a pin as a digital input before a valid input value can be read. Make sure to disable the analog output function on the pin if any is present. Digital Output 0 0 TABLE 10-2: INPUT VOLTAGE LEVELS FOR PORT OR PIN TOLERATED DESCRIPTION INPUT Tolerated Input Description Port or Pin PORTA(1)<10:9, 7:6> PORTB<15:0> PORTC(1)<15:12, 4> PORTD<7:6> VDD Only VDD input levels are tolerated. PORTE(1)<9> PORTF<0> PORTG<9:6, 3:2> PORTA(1)<15:14, 5:0> PORTC(1)<3:1> PORTD(1)<15:8, 5:0> Tolerates input levels above VDD, useful 5.5V for most standard logic. PORTE(1)<8:0> PORTF(1)<13:12, 8:7, 5:1> PORTG(1)<15:12, 1:0> Note 1: Not all of the pins of these PORTS are implemented in 64-pin devices (PIC24FJXXXDAX06); refer to the device pinout diagrams for the details. DS39969B-page 158 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-1: U-0 -- bit 15 R/W-1 ANSA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 ANSA6 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 ANSA10 R/W-1 ANSA9 U-0 -- bit 8 Unimplemented: Read as `0' ANSA<10:9>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled Unimplemented: Read as `0' ANSA<7:6>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled Unimplemented: Read as `0' This register is not available on 64-pin devices (PIC24FJXXXDAX06). bit 8 bit 7-6 bit 5-0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 159 PIC24FJ256DA210 FAMILY REGISTER 10-2: R/W-1 ANSB15 bit 15 R/W-1 ANSB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 ANSB6 R/W-1 ANSB5 R/W-1 ANSB4 R/W-1 ANSB3 R/W-1 ANSB2 R/W-1 ANSB1 ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER R/W-1 ANSB13 R/W-1 ANSB12 R/W-1 ANSB11 R/W-1 ANSB10 R/W-1 ANSB9 R/W-1 ANSB8 bit 8 R/W-1 ANSB0 bit 0 R/W-1 ANSB14 ANSB<15:0>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled REGISTER 10-3: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-13 ANSC: PORTC ANALOG FUNCTION SELECTION REGISTER R/W-1 ANSC13 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- R/W-1 ANSC4(1) U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-1 ANSC14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' ANSC<14:13>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled Unimplemented: Read as `0' ANSC4: Analog Function Selection bit(1) 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled Unimplemented: Read as `0' This bit is not available on 64-pin devices (PIC24FJXXXDAX06). bit 12-5 bit 4 bit 3-0 Note 1: DS39969B-page 160 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-4: U-0 -- bit 15 R/W-1 ANSD7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 ANSD6 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 ANSD: PORTD ANALOG FUNCTION SELECTION REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 Unimplemented: Read as `0' ANSD<7:6>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled Unimplemented: Read as `0' bit 5-0 REGISTER 10-5: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 ANSE: PORTE ANALOG FUNCTION SELECTION REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 ANSE9 U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' ANSE9: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled Unimplemented: Read as `0' This register is not available in 64-pin devices (PIC24FJXXXDAX06). bit 8-0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 161 PIC24FJ256DA210 FAMILY REGISTER 10-6: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- ANSF: PORTF ANALOG FUNCTION SELECTION REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 ANSF0 bit 0 Unimplemented: Read as `0' ANSF0: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled REGISTER 10-7: U-0 -- bit 15 R/W-1 ANSG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-6 ANSG: PORTG ANALOG FUNCTION SELECTION REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 ANSG9 R/W-1 ANSG8 bit 8 R/W-1 ANSG6 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' ANSG<9:6>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled Unimplemented: Read as `0' bit 5-0 DS39969B-page 162 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ256DA210 family of devices to generate interrupt requests to the processor in response to a Change-Of-State (COS) on selected input pins. This feature is capable of detecting input Change-Of-States, even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 84 external inputs that may be selected (enabled) for generating an interrupt request on a Change-Of-State. Registers, CNEN1 through CNEN6, contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin has a both a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source that is connected to the pin, while the pull-downs act as a current sink that is connected to the pin. These eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups and pull-downs are separately enabled using the CNPU1 through CNPU6 registers (for pull-ups), and the CNPD1 through CNPD6 registers (for pull-downs). Each CN pin has individual control bits for its pull-up and pull-down. Setting a control bit enables the weak pull-up or pull-down for the corresponding pin. When the internal pull-up is selected, the pin pulls up to VDD - 1.1V (typical). When the internal pull-down is selected, the pin pulls down to VSS. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Note: To use CN83 and CN84, which are on the D+ and D- pins, the UTRDIS bit (U1CNFG2<0>) should be set. EXAMPLE 10-1: MOV MOV NOP BTSS 0xFF00, W0 W0, TRISB PORTB, #13 PORT WRITE/READ IN ASSEMBLY ; ; ; ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction EXAMPLE 10-2: PORT WRITE/READ IN `C' // Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs // Delay 1 cycle // Next Instruction TRISB = 0xFF00; Nop(); If (PORTBbits.RB13){ }; 2010 Microchip Technology Inc. DS39969B-page 163 PIC24FJ256DA210 FAMILY 10.4 Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient work arounds in application code or a complete redesign may be the only option. The Peripheral Pin Select (PPS) feature provides an alternative to these choices by enabling the user's peripheral set selection and its placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The Peripheral Pin Select feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of any one of many digital peripherals to any one of these I/O pins. PPS is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. A key difference between pin select and non-pin select peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 10.4.2.1 Peripheral Pin Select Function Priority Pin-selectable peripheral outputs (e.g., OC, UART transmit) will take priority over general purpose digital functions on a pin, such as EPMP and port I/O. Specialized digital outputs, such as USB functionality, will take priority over PPS outputs on the same pin. The pin diagrams list peripheral outputs in the order of priority. Refer to them for priority concerns on a particular pin. Unlike PIC24F devices with fixed peripherals, pin selectable peripheral inputs will never take ownership of a pin. The pin's output buffer will be controlled by the TRISx setting or by a fixed peripheral on the pin. If the pin is configured in digital mode then the PPS input will operate correctly. If an analog function is enabled on the pin the PPS input will be disabled. 10.4.1 AVAILABLE PINS 10.4.3 The PPS feature is used with a range of up to 44 pins, depending on the particular device and its pin count. Pins that support the Peripheral Pin Select feature include the designation, "RPn" or "RPIn", in their full pin designation, where "n" is the remappable pin number. "RP" is used to designate pins that support both remappable input and output functions, while "RPI" indicates pins that support remappable input functions only. PIC24FJ256DA210 family devices support a larger number of remappable input only pins than remappable input/output pins. In this device family, there are up to 32 remappable input/output pins, depending on the pin count of the particular device selected; these are numbered, RP0 through RP31. Remappable input only pins are numbered above this range, from RPI32 to RPI43 (or the upper limit for that particular device). See Table 1-1 for a summary of pinout options in each package offering. CONTROLLING PERIPHERAL PIN SELECT PPS features are controlled through two sets of Special Function Registers (SFRs): one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on if an input or an output is being mapped. 10.4.3.1 Input Mapping 10.4.2 AVAILABLE PERIPHERALS The peripherals managed by the PPS are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. PPS is not available for I2CTM, change notification inputs, RTCC alarm outputs, EPMP signals, graphics controller signals or peripherals with analog inputs. The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 10-8 through Register 10-28). Each register contains two sets of 6-bit fields, with each set associated with one of the pin-selectable peripherals. Programming a given peripheral's bit field with an appropriate 6-bit value maps the RPn/RPIn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of Peripheral Pin Selections supported by the device. DS39969B-page 164 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 10-3: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Name INT1 INT2 INT3 INT4 IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 OCFA OCFB SCK1IN SDI1 SS1IN SCK2IN SDI2 SS2IN SCK3IN SDI3 SS3IN T2CK T3CK T4CK T5CK U1CTS U1RX U2CTS U2RX U3CTS U3RX U4CTS U4RX Register RPINR0 RPINR1 RPINR1 RPINR2 RPINR7 RPINR7 RPINR8 RPINR8 RPINR9 RPINR9 RPINR10 RPINR10 RPINR15 RPINR11 RPINR11 RPINR20 RPINR20 RPINR21 RPINR22 RPINR22 RPINR23 RPINR28 RPINR28 RPINR29 RPINR3 RPINR3 RPINR4 RPINR4 RPINR18 RPINR18 RPINR19 RPINR19 RPINR21 RPINR17 RPINR27 RPINR27 Function Mapping Bits INT1R<5:0> INT2R<5:0> INT3R<5:0> INT4R<5:0> IC1R<5:0> IC2R<5:0> IC3R<5:0> IC4R<5:0> IC5R<5:0> IC6R<5:0> IC7R<5:0> IC8R<5:0> IC9R<5:0> OCFAR<5:0> OCFBR<5:0> SCK1R<5:0> SDI1R<5:0> SS1R<5:0> SCK2R<5:0> SDI2R<5:0> SS2R<5:0> SCK3R<5:0> SDI3R<5:0> SS3R<5:0> T2CKR<5:0> T3CKR<5:0> T4CKR<5:0> T5CKR<5:0> U1CTSR<5:0> U1RXR<5:0> U2CTSR<5:0> U2RXR<5:0> U3CTSR<5:0> U3RXR<5:0> U4CTSR<5:0> U4RXR<5:0> Input Name External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Capture 6 Input Capture 7 Input Capture 8 Input Capture 9 Output Compare Fault A Output Compare Fault B SPI1 Clock Input SPI1 Data Input SPI1 Slave Select Input SPI2 Clock Input SPI2 Data Input SPI2 Slave Select Input SPI3 Clock Input SPI3 Data Input SPI3 Slave Select Input Timer2 External Clock Timer3 External Clock Timer4 External Clock Timer5 External Clock UART1 Clear To Send UART1 Receive UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers. 2010 Microchip Technology Inc. DS39969B-page 165 PIC24FJ256DA210 FAMILY 10.4.3.2 Output Mapping In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Each register contains two 6-bit fields, with each field being associated with one RPn pin (see Register 10-29 through Register 10-44). The value of the bit field corresponds to one of the peripherals and that peripheral's output is mapped to the pin (see Table 10-4). Because of the mapping technique, the list of peripherals for output mapping also includes a null value of `000000'. This permits any given pin to remain disconnected from the output of any of the pin-selectable peripherals. TABLE 10-4: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Function NULL(2) C1OUT C2OUT U1TX U1RTS U2RTS (3) Output Function Number(1) 0 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37-63 Note 1: 2: 3: Output Name Null Comparator 1 Output Comparator 2 Output UART1 Transmit UART1 Request To Send UART2 Transmit UART2 Request To Send SPI1 Data Output SPI1 Clock Output SPI1 Slave Select Output SPI2 Data Output SPI2 Clock Output SPI2 Slave Select Output Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Output Compare 6 Output Compare 7 Output Compare 8 UART3 Transmit UART3 Request To Send UART4 Transmit UART4 Request To Send SPI3 Data Output SPI3 Clock Output SPI3 Slave Select Output Output Compare 9 Comparator 3 Output NC U2TX (3) SDO1 SCK1OUT SS1OUT SDO2 SCK2OUT SS2OUT OC1 OC2 OC3 OC4 OC5 OC6 OC7 OC8 U3TX U3RTS U4RTS (3) U4TX (3) SDO3 SCK3OUT SS3OUT OC9 C3OUT (unused) Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. IrDA(R) BCLK functionality uses this output. DS39969B-page 166 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 10.4.3.3 Mapping Limitations 10.4.4.1 Control Register Lock The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention, caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lock outs. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON<6>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 46h to OSCCON<7:0>. Write 57h to OSCCON<7:0>. Clear (or set) IOLOCK as a single operation. 10.4.3.4 Mapping Exceptions for PIC24FJ256DA210 Devices Although the PPS registers theoretically allow for up to 64 remappable I/O pins, not all of these are implemented in all devices. For PIC24FJ256DA210 family devices, the maximum number of remappable pins available are 44, which includes 12 input only pins. In addition, some pins in the RP and RPI sequences are unimplemented in lower pin count devices. The differences in available remappable pins are summarized in Table 10-5. When developing applications that use remappable pins, users should also keep these things in mind: * For the RPINRx registers, bit combinations corresponding to an unimplemented pin for a particular device are treated as invalid; the corresponding module will not have an input mapped to it. For all PIC24FJ256DA210 family devices, this includes all values greater than 43 (`101011'). * For RPORx registers, the bit fields corresponding to an unimplemented pin will also be unimplemented. Writing to these fields will have no effect. Unlike the similar sequence with the oscillator's LOCK bit, IOLOCK remains in one state until changed. This allows all of the Peripheral Pin Selects to be configured with a single unlock sequence, followed by an update to all control registers, then locked with a second lock sequence. 10.4.4.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. 10.4.4.3 Configuration Bit Pin Select Lock 10.4.4 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24F devices include three features to prevent alterations to the peripheral map: * Control register lock sequence * Continuous state monitoring * Configuration bit remapping lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CW2<4>) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. TABLE 10-5: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ256DA210 FAMILY DEVICES RP Pins (I/O) Total 28 32 Unimplemented RP5, RP15, RP30, RP31 -- Total 1 12 RPI Pins Unimplemented RPI32-36, RPI38-43 -- Device Pin Count 64-Pin (PIC24FJXXXDAX06) 100/121-Pin (PIC24FJXXXDAX10) 2010 Microchip Technology Inc. DS39969B-page 167 PIC24FJ256DA210 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control Peripheral Pin Selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device's default (Reset) state. Since all RPINRx registers reset to `111111' and all RPORx registers reset to `000000', all Peripheral Pin Select inputs are tied to VSS and all Peripheral Pin Select outputs are disconnected. Note: In tying Peripheral Pin Select inputs to RP63, RP63 need not exist on a device for the registers to be reset to it. Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation, and enabled as if it were tied to a fixed pin. Where this happens in the application code (immediately following device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that Peripheral Pin Select functions neither override analog inputs nor reconfigure pins with analog functions for digital I/O. If a pin is configured as an analog input on device Reset, it must be explicitly reconfigured as digital I/O when used with a Peripheral Pin Select. Example 10-3 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: * Input Functions: U1RX, U1CTS * Output Functions: U1TX, U1RTS This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. Because the unlock sequence is timing-critical, it must be executed as an assembly language routine in the same manner as changes to the oscillator configuration. If the bulk of the application is written in `C', or another high-level language, the unlock sequence should be performed by writing in-line assembly. Choosing the configuration requires the review of all Peripheral Pin Selects and their pin assignments, especially those that will not be used in the application. In all cases, unused pin-selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn/RPIn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin's I/O circuitry. In theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. EXAMPLE 10-3: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS \n" \n" \n" \n" \n" // Unlock Registers asm volatile( "MOV #OSCCON, w1 "MOV #0x46, w2 "MOV #0x57, w3 "MOV.b w2, [w1] "MOV.b w3, [w1] "BCLR OSCCON,#6"); // or use C30 built-in macro: // __builtin_write_OSCCONL(OSCCON & 0xbf); // Configure Input Functions (Table 10-2)) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions (Table 10-4) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; // Lock Registers asm volatile ("MOV "MOV "MOV "MOV.b "MOV.b "BSET #OSCCON, w1 #0x46, w2 #0x57, w3 w2, [w1]\ w3, [w1] OSCCON, #6") \n" \n" \n" n" \n" ; // or use C30 built-in macro: // __builtin_write_OSCCONL(OSCCON | 0x40); DS39969B-page 168 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 10.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ256DA210 family of devices implements a total of 37 registers for remappable peripheral configuration: * Input Remappable Peripheral Registers (21) * Output Remappable Peripheral Registers (16) Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. See Section 10.4.4.1 "Control Register Lock" for a specific command sequence. REGISTER 10-8: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-0 RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 -- R/W-1 INT1R5 R/W-1 INT1R4 R/W-1 INT1R3 R/W-1 INT1R2 R/W-1 INT1R1 R/W-1 INT1R0 bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' INT1R<5:0>: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' REGISTER 10-9: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 -- R/W-1 INT3R5 R/W-1 INT3R4 R/W-1 INT3R3 R/W-1 INT3R2 R/W-1 INT3R1 R/W-1 INT3R0 bit 8 U-0 -- R/W-1 INT2R5 R/W-1 INT2R4 R/W-1 INT2R3 R/W-1 INT2R2 R/W-1 INT2R1 R/W-1 INT2R0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. DS39969B-page 169 PIC24FJ256DA210 FAMILY REGISTER 10-10: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 INT4R5 R/W-1 INT4R4 R/W-1 INT4R3 R/W-1 INT4R2 R/W-1 INT4R1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 INT4R0 bit 0 Unimplemented: Read as `0' INT4R<5:0>: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits REGISTER 10-11: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 T2CKR5 R/W-1 T2CKR4 R/W-1 T2CKR3 R/W-1 T2CKR2 R/W-1 T2CKR1 U-0 -- R/W-1 T3CKR5 R/W-1 T3CKR4 R/W-1 T3CKR3 R/W-1 T3CKR2 R/W-1 T3CKR1 R/W-1 T3CKR0 bit 8 R/W-1 T2CKR0 bit 0 Unimplemented: Read as `0' T3CKR<5:0>: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits DS39969B-page 170 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-12: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 T4CKR5 R/W-1 T4CKR4 R/W-1 T4CKR3 R/W-1 T4CKR2 R/W-1 T4CKR1 U-0 -- R/W-1 T5CKR5 R/W-1 T5CKR4 R/W-1 T5CKR3 R/W-1 T5CKR2 R/W-1 T5CKR1 R/W-1 T5CKR0 bit 8 R/W-1 T4CKR0 bit 0 Unimplemented: Read as `0' T5CKR<5:0>: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' T4CKR<5:0>: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits REGISTER 10-13: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 IC1R5 R/W-1 IC1R4 R/W-1 IC1R3 R/W-1 IC1R2 R/W-1 IC1R1 U-0 -- R/W-1 IC2R5 R/W-1 IC2R4 R/W-1 IC2R3 R/W-1 IC2R2 R/W-1 IC2R1 R/W-1 IC2R0 bit 8 R/W-1 IC1R0 bit 0 Unimplemented: Read as `0' IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. DS39969B-page 171 PIC24FJ256DA210 FAMILY REGISTER 10-14: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 IC3R5 R/W-1 IC3R4 R/W-1 IC3R3 R/W-1 IC3R2 R/W-1 IC3R1 U-0 -- R/W-1 IC4R5 R/W-1 IC4R4 R/W-1 IC4R3 R/W-1 IC4R2 R/W-1 IC4R1 R/W-1 IC4R0 bit 8 R/W-1 IC3R0 bit 0 Unimplemented: Read as `0' IC4R<5:0>: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' IC3R<5:0>: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits REGISTER 10-15: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 IC5R5 R/W-1 IC5R4 R/W-1 IC5R3 R/W-1 IC5R2 R/W-1 IC5R1 U-0 -- R/W-1 IC6R5 R/W-1 IC6R4 R/W-1 IC6R3 R/W-1 IC6R2 R/W-1 IC6R1 R/W-1 IC6R0 bit 8 R/W-1 IC5R0 bit 0 Unimplemented: Read as `0' IC6R<5:0>: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' IC5R<5:0>: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits DS39969B-page 172 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-16: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 IC7R5 R/W-1 IC7R4 R/W-1 IC7R3 R/W-1 IC7R2 R/W-1 IC7R1 U-0 -- R/W-1 IC8R5 R/W-1 IC8R4 R/W-1 IC8R3 R/W-1 IC8R2 R/W-1 IC8R1 R/W-1 IC8R0 bit 8 R/W-1 IC7R0 bit 0 Unimplemented: Read as `0' IC8R<5:0>: Assign Input Capture 8 (IC8) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' IC7R<5:0>: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits REGISTER 10-17: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 OCFAR5 R/W-1 OCFAR4 R/W-1 OCFAR3 R/W-1 OCFAR2 R/W-1 OCFAR1 U-0 -- R/W-1 OCFBR5 R/W-1 OCFBR4 R/W-1 OCFBR3 R/W-1 OCFBR2 R/W-1 OCFBR1 R/W-1 OCFBR0 bit 8 R/W-1 OCFAR0 bit 0 Unimplemented: Read as `0' OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. DS39969B-page 173 PIC24FJ256DA210 FAMILY REGISTER 10-18: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 U-0 -- R/W-1 IC9R5 R/W-1 IC9R4 R/W-1 IC9R3 R/W-1 IC9R2 R/W-1 IC9R1 R/W-1 IC9R0 bit 8 Unimplemented: Read as `0' IC9R<5:0>: Assign Input Capture 9 (IC9) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' REGISTER 10-19: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 U-0 -- R/W-1 U3RXR5 R/W-1 U3RXR4 R/W-1 U3RXR3 R/W-1 U3RXR2 R/W-1 U3RXR1 R/W-1 U3RXR0 bit 8 Unimplemented: Read as `0' U3RXR<5:0>: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' DS39969B-page 174 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-20: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 U1RXR5 R/W-1 U1RXR4 R/W-1 U1RXR3 R/W-1 U1RXR2 R/W-1 U1RXR1 U-0 -- R/W-1 U1CTSR5 R/W-1 U1CTSR4 R/W-1 U1CTSR3 R/W-1 U1CTSR2 R/W-1 U1CTSR1 R/W-1 U1CTSR0 bit 8 R/W-1 U1RXR0 bit 0 Unimplemented: Read as `0' U1CTSR<5:0>: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' U1RXR<5:0>: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits REGISTER 10-21: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 U2RXR5 R/W-1 U2RXR4 R/W-1 U2RXR3 R/W-1 U2RXR2 R/W-1 U2RXR1 U-0 -- R/W-1 U2CTSR5 R/W-1 U2CTSR4 R/W-1 U2CTSR3 R/W-1 U2CTSR2 R/W-1 U2CTSR1 R/W-1 U2CTSR0 bit 8 R/W-1 U2RXR0 bit 0 Unimplemented: Read as `0' U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. DS39969B-page 175 PIC24FJ256DA210 FAMILY REGISTER 10-22: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SDI1R5 R/W-1 SDI1R4 R/W-1 SDI1R3 R/W-1 SDI1R2 R/W-1 SDI1R1 U-0 -- R/W-1 SCK1R5 R/W-1 SCK1R4 R/W-1 SCK1R3 R/W-1 SCK1R2 R/W-1 SCK1R1 R/W-1 SCK1R0 bit 8 R/W-1 SDI1R0 bit 0 Unimplemented: Read as `0' SCK1R<5:0>: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits REGISTER 10-23: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SS1R5 R/W-1 SS1R4 R/W-1 SS1R3 R/W-1 SS1R2 R/W-1 SS1R1 U-0 -- R/W-1 U3CTSR5 R/W-1 U3CTSR4 R/W-1 U3CTSR3 R/W-1 U3CTSR2 R/W-1 U3CTSR1 R/W-1 U3CTSR0 bit 8 R/W-1 SS1R0 bit 0 Unimplemented: Read as `0' U3CTSR<5:0>: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' SS1R<5:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits DS39969B-page 176 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-24: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SDI2R5 R/W-1 SDI2R4 R/W-1 SDI2R3 R/W-1 SDI2R2 R/W-1 SDI2R1 U-0 -- R/W-1 SCK2R5 R/W-1 SCK2R4 R/W-1 SCK2R3 R/W-1 SCK2R2 R/W-1 SCK2R1 R/W-1 SCK2R0 bit 8 R/W-1 SDI2R0 bit 0 Unimplemented: Read as `0' SCK2R<5:0>: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' SDI2R<5:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits REGISTER 10-25: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SS2R5 R/W-1 SS2R4 R/W-1 SS2R3 R/W-1 SS2R2 R/W-1 SS2R1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 SS2R0 bit 0 Unimplemented: Read as `0' SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. DS39969B-page 177 PIC24FJ256DA210 FAMILY REGISTER 10-26: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 U4RXR5 R/W-1 U4RXR4 R/W-1 U4RXR3 R/W-1 U4RXR2 R/W-1 U4RXR1 U-0 -- R/W-1 U4CTSR5 R/W-1 U4CTSR4 R/W-1 U4CTSR3 R/W-1 U4CTSR2 R/W-1 U4CTSR1 R/W-1 U4CTSR0 bit 8 R/W-1 U4RXR0 bit 0 Unimplemented: Read as `0' U4CTSR<5:0>: Assign UART4 Clear to Send (U4CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' U4RXR<5:0>: Assign UART4 Receive (U4RX) to Corresponding RPn or RPIn Pin bits REGISTER 10-27: RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SDI3R5 R/W-1 SDI3R4 R/W-1 SDI3R3 R/W-1 SDI3R2 R/W-1 SDI3R1 U-0 -- R/W-1 SCK3R5 R/W-1 SCK3R4 R/W-1 SCK3R3 R/W-1 SCK3R2 R/W-1 SCK3R1 R/W-1 SCK3R0 bit 8 R/W-1 SDI3R0 bit 0 Unimplemented: Read as `0' SCK3R<5:0>: Assign SPI3 Clock Input (SCK3IN) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as `0' SDI3R<5:0>: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits DS39969B-page 178 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-28: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-1 SS3R5 R/W-1 SS3R4 R/W-1 SS3R3 R/W-1 SS3R2 R/W-1 SS3R1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-1 SS3R0 bit 0 Unimplemented: Read as `0' SS3R<5:0>: Assign SPI3 Slave Select Input (SS31IN) to Corresponding RPn or RPIn Pin bits 2010 Microchip Technology Inc. DS39969B-page 179 PIC24FJ256DA210 FAMILY REGISTER 10-29: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP0R5 R/W-0 RP0R4 R/W-0 RP0R3 R/W-0 RP0R2 R/W-0 RP0R1 U-0 -- R/W-0 RP1R5 R/W-0 RP1R4 R/W-0 RP1R3 R/W-0 RP1R2 R/W-0 RP1R1 R/W-0 RP1R0 bit 8 R/W-0 RP0R0 bit 0 Unimplemented: Read as `0' RP1R<5:0>: RP1 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP1 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP0R<5:0>: RP0 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP0 (see Table 10-4 for peripheral function numbers). REGISTER 10-30: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP2R5 R/W-0 RP2R4 R/W-0 RP2R3 R/W-0 RP2R2 R/W-0 RP2R1 U-0 -- R/W-0 RP3R5 R/W-0 RP3R4 R/W-0 RP3R3 R/W-0 RP3R2 R/W-0 RP3R1 R/W-0 RP3R0 bit 8 R/W-0 RP2R0 bit 0 Unimplemented: Read as `0' RP3R<5:0>: RP3 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP3 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP2R<5:0>: RP2 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP2 (see Table 10-4 for peripheral function numbers). DS39969B-page 180 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-31: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP4R5 R/W-0 RP4R4 R/W-0 RP4R3 R/W-0 RP4R2 R/W-0 RP4R1 U-0 -- R/W-0 RP5R5(1) R/W-0 RP5R4(1) R/W-0 RP5R3(1) R/W-0 RP5R2(1) R/W-0 RP5R1(1) R/W-0 RP5R0(1) bit 8 R/W-0 RP4R0 bit 0 Unimplemented: Read as `0' RP5R<5:0>: RP5 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP5 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP4R<5:0>: RP4 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP4 (see Table 10-4 for peripheral function numbers). Unimplemented in 64-pin devices; read as `0'. Note 1: REGISTER 10-32: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP6R5 R/W-0 RP6R4 R/W-0 RP6R3 R/W-0 RP6R2 R/W-0 RP6R1 U-0 -- R/W-0 RP7R5 R/W-0 RP7R4 R/W-0 RP7R3 R/W-0 RP7R2 R/W-0 RP7R1 R/W-0 RP7R0 bit 8 R/W-0 RP6R0 bit 0 Unimplemented: Read as `0' RP7R<5:0>: RP7 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP7 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP6R<5:0>: RP6 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP6 (see Table 10-4 for peripheral function numbers). 2010 Microchip Technology Inc. DS39969B-page 181 PIC24FJ256DA210 FAMILY REGISTER 10-33: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP8R5 R/W-0 RP8R4 R/W-0 RP8R3 R/W-0 RP8R2 R/W-0 RP8R1 U-0 -- R/W-0 RP9R5 R/W-0 RP9R4 R/W-0 RP9R3 R/W-0 RP9R2 R/W-0 RP9R1 R/W-0 RP9R0 bit 8 R/W-0 RP8R0 bit 0 Unimplemented: Read as `0' RP9R<5:0>: RP9 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP9 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP8R<5:0>: RP8 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP8 (see Table 10-4 for peripheral function numbers). REGISTER 10-34: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP10R5 R/W-0 RP10R4 R/W-0 RP10R3 R/W-0 RP10R2 R/W-0 RP10R1 U-0 -- R/W-0 RP11R5 R/W-0 RP11R4 R/W-0 RP11R3 R/W-0 RP11R2 R/W-0 RP11R1 R/W-0 RP11R0 bit 8 R/W-0 RP10R0 bit 0 Unimplemented: Read as `0' RP11R<5:0>: RP11 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP11 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP10R<5:0>: RP10 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP10 (see Table 10-4 for peripheral function numbers). DS39969B-page 182 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-35: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP12R5 R/W-0 RP12R4 R/W-0 RP12R3 R/W-0 RP12R2 R/W-0 RP12R1 U-0 -- R/W-0 RP13R5 R/W-0 RP13R4 R/W-0 RP13R3 R/W-0 RP13R2 R/W-0 RP13R1 R/W-0 RP13R0 bit 8 R/W-0 RP12R0 bit 0 Unimplemented: Read as `0' RP13R<5:0>: RP13 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP13 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP12R<5:0>: RP12 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP12 (see Table 10-4 for peripheral function numbers). REGISTER 10-36: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP14R5 R/W-0 RP14R4 R/W-0 RP14R3 R/W-0 RP14R2 R/W-0 RP14R1 U-0 -- R/W-0 RP15R5(1) R/W-0 RP15R4(1) R/W-0 RP15R3(1) R/W-0 RP15R2(1) R/W-0 RP15R1(1) R/W-0 RP15R0(1) bit 8 R/W-0 RP14R0 bit 0 Unimplemented: Read as `0' RP15R<5:0>: RP15 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP0 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP14 (see Table 10-4 for peripheral function numbers). Unimplemented in 64-pin devices; read as `0'. Note 1: 2010 Microchip Technology Inc. DS39969B-page 183 PIC24FJ256DA210 FAMILY REGISTER 10-37: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP16R5 R/W-0 RP16R4 R/W-0 RP16R3 R/W-0 RP16R2 R/W-0 RP16R1 U-0 -- R/W-0 RP17R5 R/W-0 RP17R4 R/W-0 RP17R3 R/W-0 RP17R2 R/W-0 RP17R1 R/W-0 RP17R0 bit 8 R/W-0 RP16R0 bit 0 Unimplemented: Read as `0' RP17R<5:0>: RP17 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP17 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP16R<5:0>: RP16 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP16 (see Table 10-4 for peripheral function numbers). REGISTER 10-38: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP18R5 R/W-0 RP18R4 R/W-0 RP18R3 R/W-0 RP18R2 R/W-0 RP18R1 U-0 -- R/W-0 RP19R5 R/W-0 RP19R4 R/W-0 RP19R3 R/W-0 RP19R2 R/W-0 RP19R1 R/W-0 RP19R0 bit 8 R/W-0 RP18R0 bit 0 Unimplemented: Read as `0' RP19R<5:0>: RP19 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP19 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP18R<5:0>: RP18 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP18 (see Table 10-4 for peripheral function numbers). DS39969B-page 184 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-39: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP20R5 R/W-0 RP20R4 R/W-0 RP20R3 R/W-0 RP20R2 R/W-0 RP20R1 U-0 -- R/W-0 RP21R5 R/W-0 RP21R4 R/W-0 RP21R3 R/W-0 RP21R2 R/W-0 RP21R1 R/W-0 RP21R0 bit 8 R/W-0 RP20R0 bit 0 Unimplemented: Read as `0' RP21R<5:0>: RP21 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP21 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP20R<5:0>: RP20 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP20 (see Table 10-4 for peripheral function numbers). REGISTER 10-40: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP22R5 R/W-0 RP22R4 R/W-0 RP22R3 R/W-0 RP22R2 R/W-0 RP22R1 U-0 -- R/W-0 RP23R5 R/W-0 RP23R4 R/W-0 RP23R3 R/W-0 RP23R2 R/W-0 RP23R1 R/W-0 RP23R0 bit 8 R/W-0 RP22R0 bit 0 Unimplemented: Read as `0' RP23R<5:0>: RP23 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP23 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP22 (see Table 10-4 for peripheral function numbers). 2010 Microchip Technology Inc. DS39969B-page 185 PIC24FJ256DA210 FAMILY REGISTER 10-41: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP24R5 R/W-0 RP24R4 R/W-0 RP24R3 R/W-0 RP24R2 R/W-0 RP24R1 U-0 -- R/W-0 RP25R5 R/W-0 RP25R4 R/W-0 RP25R3 R/W-0 RP25R2 R/W-0 RP25R1 R/W-0 RP25R0 bit 8 R/W-0 RP24R0 bit 0 Unimplemented: Read as `0' RP25R<5:0>: RP25 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP25 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP24R<5:0>: RP24 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP24 (see Table 10-4 for peripheral function numbers). REGISTER 10-42: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP26R5 R/W-0 RP26R4 R/W-0 RP26R3 R/W-0 RP26R2 R/W-0 RP26R1 U-0 -- R/W-0 RP27R5 R/W-0 RP27R4 R/W-0 RP27R3 R/W-0 RP27R2 R/W-0 RP27R1 R/W-0 RP27R0 bit 8 R/W-0 RP26R0 bit 0 Unimplemented: Read as `0' RP27R<5:0>: RP27 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP27 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP26R<5:0>: RP26 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP26 (see Table 10-4 for peripheral function numbers). DS39969B-page 186 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 10-43: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP28R5 R/W-0 RP28R4 R/W-0 RP28R3 R/W-0 RP28R2 R/W-0 RP28R1 U-0 -- R/W-0 RP29R5 R/W-0 RP29R4 R/W-0 RP29R3 R/W-0 RP29R2 R/W-0 RP29R1 R/W-0 RP29R0 bit 8 R/W-0 RP28R0 bit 0 Unimplemented: Read as `0' RP29R<5:0>: RP29 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP29 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP28R<5:0>: RP28 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP28 (see Table 10-4 for peripheral function numbers). REGISTER 10-44: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15(1) U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 RP30R5 R/W-0 RP30R4 R/W-0 RP30R3 R/W-0 RP30R2 R/W-0 RP30R1 U-0 -- R/W-0 RP31R5 R/W-0 RP31R4 R/W-0 RP31R3 R/W-0 RP31R2 R/W-0 RP31R1 R/W-0 RP31R0 bit 8 R/W-0 RP30R0 bit 0 Unimplemented: Read as `0' RP31R<5:0>: RP31 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP31 (see Table 10-4 for peripheral function numbers). Unimplemented: Read as `0' RP30R<5:0>: RP30 Output Pin Mapping bits(1) Peripheral output number n is assigned to pin, RP30 (see Table 10-4 for peripheral function numbers). Unimplemented in 64-pin devices; read as `0'. Note 1: 2010 Microchip Technology Inc. DS39969B-page 187 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 188 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 11.0 Note: TIMER1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 14. "Timers" (DS39704). The information in this data sheet supersedes the information in the FRM. Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. 2. 3. 4. 5. 6. Set the TON bit (= 1). Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. Load the timer period value into the PR1 register. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP<2:0>, to set the interrupt priority. The Timer1 module is a 16-bit timer, which can serve as the time counter for the Real-Time Clock (RTC) or operate as a free-running, interval timer/counter. Timer1 can operate in three modes: * 16-Bit Timer * 16-Bit Synchronous Counter * 16-Bit Asynchronous Counter Timer1 also supports these features: * Timer Gate Operation * Selectable Prescaler Settings * Timer Operation during CPU Idle and Sleep modes * Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS<1:0> SOSCO/ T1CK SOSCEN SOSCI Gate Sync TCY TGATE TON 1x 01 00 TGATE TCS Q Q Reset D CK 0 TMR1 1 Comparator TSYNC Sync 2 Prescaler 1, 8, 64, 256 Set T1IF 1 0 Equal PR1 2010 Microchip Technology Inc. DS39969B-page 189 PIC24FJ256DA210 FAMILY REGISTER 11-1: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 U-0 -- R/W-0 TSYNC R/W-0 TCS U-0 -- bit 0 T1CON: TIMER1 CONTROL REGISTER(1) U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39969B-page 190 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 12.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 14. "Timers" (DS39704). The information in this data sheet supersedes the information in the FRM. To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. 2. 3. Set the T32 bit (T2CON<3> or T4CON<3> = 1). Select the prescaler ratio for Timer2 or Timer4 using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. If TCS is set to an external clock, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. For more information, see Section 10.4 "Peripheral Pin Select (PPS)". Load the timer period value. PR3 (or PR5) will contain the most significant word (msw) of the value while PR2 (or PR4) contains the least significant word (lsw). If interrupts are required, set the interrupt enable bit, T3IE or T5IE; use the priority bits, T3IP<2:0> or T5IP<2:0>, to set the interrupt priority. Note that while Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 interrupt. Set the TON bit (= 1). The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent, 16-bit timers with selectable operating modes. As 32-bit timers, Timer2/3 and Timer4/5 can each operate in three modes: * Two independent 16-bit timers with all 16-bit operating modes (except Asynchronous Counter mode) * Single 32-bit timer * Single 32-bit synchronous counter They also support these features: * * * * * Timer Gate Operation Selectable Prescaler Settings Timer Operation during Idle and Sleep modes Interrupt on a 32-Bit Period Register Match ADC Event Trigger (only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode) 4. 5. 6. The timer value, at any point, is stored in the register pair, TMR<3:2> (or TMR<5:4>). TMR3 (TMR5) always contains the most significant word of the count, while TMR2 (TMR4) contains the least significant word. To configure any of the timers for individual 16-bit operation: 1. Clear the T32 bit corresponding to that timer (T2CON<3> for Timer2 and Timer3 or T4CON<3> for Timer4 and Timer5). Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE; use the priority bits, TxIP<2:0>, to set the interrupt priority. Set the TON (TxCON<15> = 1) bit. Individually, all four of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the ADC Event Trigger; this is implemented only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, T4CON and T5CON registers. T2CON and T4CON are shown in generic form in Register 12-1; T3CON and T5CON are shown in Register 12-2. For 32-bit timer/counter operation, Timer2 and Timer4 are the least significant word; Timer3 and Timer4 are the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. 2. 3. 4. 5. 6. 2010 Microchip Technology Inc. DS39969B-page 191 PIC24FJ256DA210 FAMILY FIGURE 12-1: T2CK (T4CK) Gate Sync TCY TGATE TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TON 1x Prescaler 1, 8, 64, 256 TCKPS<1:0> 2 01 00 TGATE(2) TCS(2) 1 Set T3IF (T5IF) 0 PR3 (PR5) ADC Event Trigger(3) Equal MSB Reset 16 Read TMR2 (TMR4)(1) 16 Write TMR2 (TMR4)(1) TMR3 (TMR5) Q Q D CK PR2 (PR4) Comparator LSB TMR2 (TMR4) Sync TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note 1: 2: 3: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39969B-page 192 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 12-2: T2CK (T4CK) Gate Sync TGATE TCY 1 Set T2IF (T4IF) 0 Reset Q Q D CK TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON 1x Prescaler 1, 8, 64, 256 TCKPS<1:0> 2 01 00 TCS(1) TGATE(1) TMR2 (TMR4) Sync Equal Comparator PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM TON 1x Prescaler 1, 8, 64, 256 TCKPS<1:0> 2 T3CK (T5CK) Sync 01 00 TCY 1 Set T3IF (T5IF) 0 Reset Q Q D CK TCS(1) TGATE(1) TGATE TMR3 (TMR5) ADC Event Trigger(2) Equal Comparator PR3 (PR5) Note 1: 2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. The ADC event trigger is available only on Timer3. 2010 Microchip Technology Inc. DS39969B-page 193 PIC24FJ256DA210 FAMILY REGISTER 12-1: R/W-0 TON bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE R/W-0 TCKPS1 R/W-0 TCKPS0 R/W-0 T32(1) U-0 -- R/W-0 TCS(2) U-0 -- bit 0 TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3) U-0 -- R/W-0 TSIDL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON<3> = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 T32: 32-Bit Timer Mode Select bit(1) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. Unimplemented: Read as `0' TCS: Timerx Clock Source Select bit(2) 1 = External clock from pin, TxCK (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. For more information, see Section 10.4 "Peripheral Pin Select (PPS)". Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: DS39969B-page 194 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 12-2: R/W-0 TON(1) bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 TGATE (1) TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3) U-0 -- R/W-0 TSIDL(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 TCKPS1 (1) R/W-0 TCKPS0 (1) U-0 -- U-0 -- R/W-0 TCS (1,2) U-0 -- bit 0 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery Unimplemented: Read as `0' TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled TCKPS<1:0>: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Unimplemented: Read as `0' TCS: Timery Clock Source Select bit(1,2) 1 = External clock from pin, TyCK (on the rising edge) 0 = Internal clock (FOSC/2) Unimplemented: Read as `0' When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-2 bit 1 bit 0 Note 1: 2: 3: 2010 Microchip Technology Inc. DS39969B-page 195 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 196 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 13.0 Note: INPUT CAPTURE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 34. "Input Capture with Dedicated Timer" (DS39722). The information in this data sheet supersedes the information in the FRM. 13.1 13.1.1 General Operating Modes SYNCHRONOUS AND TRIGGER MODES When the input capture module operates in a free-running mode, the internal 16-bit counter, ICxTMR, counts up continuously, wrapping around from FFFFh to 0000h on each overflow, with its period synchronized to the selected external clock source. When a capture event occurs, the current 16-bit value of the internal counter is written to the FIFO buffer. In Synchronous mode, the module begins capturing events on the ICx pin as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the internal counter is reset. In Trigger mode, the module waits for a Sync event from another internal module to occur before allowing the internal counter to run. Standard, free-running operation is selected by setting the SYNCSEL bits (ICxCON2<4:0>) to `00000' and clearing the ICTRIG bit (ICxCON2<7>). Synchronous and Trigger modes are selected any time the SYNCSEL bits are set to any value except `00000'. The ICTRIG bit selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSEL bits determine the sync/trigger source. When the SYNCSEL bits are set to `00000' and ICTRIG is set, the module operates in Software Trigger mode. In this case, capture operations are started by manually setting the TRIGSTAT bit (ICxCON2<6>). Devices in the PIC24FJ256DA210 family comprise nine independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts. Key features of the input capture module include: * Hardware configurable for 32-bit operation in all modes by cascading two adjacent modules * Synchronous and Trigger modes of output compare operation, with up to 30 user-selectable sync/trigger sources available * A 4-level FIFO buffer for capturing and holding timer values for several events * Configurable interrupt generation * Up to 6 clock sources available for each module, driving a separate internal 16-bit counter The module is controlled through two registers: ICxCON1 (Register 13-1) and ICxCON2 (Register 13-2). A general block diagram of the module is shown in Figure 13-1. FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM ICM<2:0> ICI1<:0> Event and Interrupt Logic Set ICXIF ICX Pin(1) Prescaler Counter 1:1/4/16 ICTSEL<2:0> Edge Detect Logic and Clock Synchronizer Increment IC Clock Sources Clock Select ICXTMR 16 4-Level FIFO Buffer 16 Sync and Trigger Sources Sync and Trigger Logic Reset 16 ICXBUF SYNCSEL<4:0> Trigger ICOV, ICBNE System Bus Note 1: The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. 2010 Microchip Technology Inc. DS39969B-page 197 PIC24FJ256DA210 FAMILY 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs and the even module (ICy) provides the Most Significant 16 bits. Wrap-arounds of the ICx registers cause an increment of their corresponding ICy registers. Cascaded operation is configured in hardware by setting the IC32 bits (ICxCON2<8>) for both modules. For 32-bit cascaded operations, the setup procedure is slightly different: 1. Set the IC32 bits for both modules (ICyCON2<8>) and (ICxCON2<8>), enabling the even numbered module first. This ensures the modules will start functioning in unison. Set the ICTSEL and SYNCSEL bits for both modules to select the same sync/trigger and time base source. Set the even module first, then the odd module. Both modules must use the same ICTSEL and SYNCSEL settings. Clear the ICTRIG bit of the even module (ICyCON2<7>). This forces the module to run in Synchronous mode with the odd module, regardless of its trigger setting. Use the odd module's ICI bits (ICxCON1<6:5>) to set the desired interrupt frequency. Use the ICTRIG bit of the odd module (ICxCON2<7>) to configure Trigger or Synchronous mode operation. Note: For Synchronous mode operation, enable the sync source as the last step. Both input capture modules are held in Reset until the sync source is enabled. 2. 3. 13.2 Capture Operations The input capture module can be configured to capture timer values and generate interrupts on rising edges on ICx or all transitions on ICx. Captures can be configured to occur on all rising edges or just some (every 4th or 16th). Interrupts can be independently configured to generate on each event or a subset of events. To set up the module for capture operations: 1. 2. 3. Configure the ICx input for one of the available Peripheral Pin Select pins. If Synchronous mode is to be used, disable the sync source before proceeding. Make sure that any previous data has been removed from the FIFO by reading ICxBUF until the ICBNE bit (ICxCON1<3>) is cleared. Set the SYNCSEL bits (ICxCON2<4:0>) to the desired sync/trigger source. Set the ICTSEL bits (ICxCON1<12:10>) for the desired clock source. Set the ICI bits (ICxCON1<6:5>) to the desired interrupt frequency Select Synchronous or Trigger mode operation: a) Check that the SYNCSEL bits are not set to `00000'. b) For Synchronous mode, clear the ICTRIG bit (ICxCON2<7>). c) For Trigger mode, set ICTRIG, and clear the TRIGSTAT bit (ICxCON2<6>). Set the ICM bits (ICxCON1<2:0>) to the desired operational mode. Enable the selected sync/trigger source. 4. 5. 6. Use the ICM bits of the odd module (ICxCON1<2:0>) to set the desired capture mode. 4. 5. 6. 7. The module is ready to capture events when the time base and the sync/trigger source are enabled. When the ICBNE bit (ICxCON1<3>) becomes set, at least one capture value is available in the FIFO. Read input capture values from the FIFO until the ICBNE clears to `0'. For 32-bit operation, read both the ICxBUF and ICyBUF for the full 32-bit timer value (ICxBUF for the lsw, ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module's ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (performed automatically by hardware). 8. 9. DS39969B-page 198 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 13-1: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ICI1 R/W-0 ICI0 R-0, HSC ICOV R-0, HSC ICBNE R/W-0 ICM2(1) R/W-0 ICM1(1) ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 -- R/W-0 ICSIDL R/W-0 ICTSEL2 R/W-0 ICTSEL1 R/W-0 ICTSEL0 U-0 -- U-0 -- bit 8 R/W-0 ICM0(1) bit 0 Unimplemented: Read as `0' ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode ICTSEL<2:0>: Input Capture Timer Select bits 111 = System clock (FOSC/2) 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer2 000 = Timer3 Unimplemented: Read as `0' ICI<1:0>: Select Number of Captures Per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty ICM<2:0>: Input Capture Mode Select bits(1) 111 = Interrupt mode: input capture functions as an interrupt pin only when the device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Prescaler Capture mode: capture on every 16th rising edge 100 = Prescaler Capture mode: capture on every 4th rising edge 011 = Simple Capture mode: capture on every rising edge 010 = Simple Capture mode: capture on every falling edge 001 = Edge Detect Capture mode: capture on every edge (rising and falling), ICI<1:0> bits do not control interrupt generation for this mode 000 = Input capture module turned off The ICx input must also be configured to an available RPn/RPIn pin. For more information, see Section 10.4 "Peripheral Pin Select (PPS)". bit 12-10 bit 9-7 bit 6-5 bit 4 bit 3 bit 2-0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 199 PIC24FJ256DA210 FAMILY REGISTER 13-2: U-0 -- bit 15 R/W-0 ICTRIG bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 HS TRIGSTAT U-0 -- R/W-0 SYNCSEL4 R/W-1 SYNCSEL3 R/W-1 SYNCSEL2 R/W-0 SYNCSEL1 ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 IC32 bit 8 R/W-1 SYNCSEL0 bit 0 Unimplemented: Read as `0' IC32: Cascade Two IC Modules Enable bit (32-bit operation) 1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = ICx functions independently as a 16-bit module ICTRIG: ICx Sync/Trigger Select bit 1 = Trigger ICx from the source designated by the SYNCSELx bits 0 = Synchronize ICx with the source designated by the SYNCSELx bits TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running (set in hardware, can be set in software) 0 = Timer source has not been triggered and is being held clear Unimplemented: Read as `0' SYNCSEL<4:0>: Synchronization/Trigger Source Selection bits 11111 = Reserved 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(1) 11011 = A/D(1) 11010 = Comparator 3(1) 11001 = Comparator 2(1) 11000 = Comparator 1(1) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 1000x = Reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2 01011 = Timer1 01010 = Input Capture 5(2) 01001 = Output Compare 9 . . . 00010 = Output Compare 2 00001 = Output Compare 1 00000 = Not synchronized to any other module Use these inputs as trigger sources only and never as sync sources. Never use an IC module as its own trigger source, by selecting this mode. bit 7 bit 6 bit 5 bit 4-0 Note 1: 2: DS39969B-page 200 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 14.0 Note: OUTPUT COMPARE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 35. "Output Compare with Dedicated Timer" (DS39723). The information in this data sheet supersedes the information in the FRM. In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module's internal counter is reset. In Trigger mode, the module waits for a sync event from another internal module to occur before allowing the counter to run. Free-running mode is selected by default or any time that the SYNCSEL bits (OCxCON2<4:0>) are set to `00000'. Synchronous or Trigger modes are selected any time the SYNCSEL bits are set to any value except `00000'. The OCTRIG bit (OCxCON2<7>) selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSEL bits determine the sync/trigger source. Devices in the PIC24FJ256DA210 family feature all of the 9 independent output compare modules. Each of these modules offers a wide range of configuration and operating options for generating pulse trains on internal device events, and can produce pulse-width modulated waveforms for driving power applications. Key features of the output compare module include: * Hardware configurable for 32-bit operation in all modes by cascading two adjacent modules * Synchronous and Trigger modes of output compare operation, with up to 31 user-selectable trigger/sync sources available * Two separate period registers (a main register, OCxR, and a secondary register, OCxRS) for greater flexibility in generating pulses of varying widths * Configurable for single pulse or continuous pulse generation on an output event, or continuous PWM waveform generation * Up to 6 clock sources available for each module, driving a separate internal 16-bit counter 14.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own set of 16-bit timer and duty cycle registers. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd numbered module (OCx) provides the Least Significant 16 bits of the 32-bit register pairs and the even module (OCy) provides the Most Significant 16 bits. Wrap-arounds of the OCx registers cause an increment of their corresponding OCy registers. Cascaded operation is configured in hardware by setting the OC32 bit (OCxCON2<8>) for both modules. For more details on cascading, refer to the "PIC24F Family Reference Manual", Section 35. "Output Compare with Dedicated Timer". 14.1 14.1.1 General Operating Modes SYNCHRONOUS AND TRIGGER MODES When the output compare module operates in a free-running mode, the internal 16-bit counter, OCxTMR, runs counts up continuously, wrapping around from 0xFFFF to 0x0000 on each overflow, with its period synchronized to the selected external clock source. Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs. 2010 Microchip Technology Inc. DS39969B-page 201 PIC24FJ256DA210 FAMILY FIGURE 14-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT<2:0> OCFLT<2:0> DCB<1:0> Match Event OC Clock Sources Clock Select Increment Comparator OCx Pin(1) OCxCON1 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxCON2 OCxR and DCB<1:0> OCxTMR Reset Comparator Match Event OC Output and Fault Logic OCFA/OCFB(2) Match Event Trigger and Sync Sources Trigger and Sync Logic Reset OCxRS OCx Interrupt Note 1: 2: The OCx outputs must be assigned to an available RPn pin before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. The OCFA/OCFB fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. 14.2 Compare Operations 3. 4. 5. 6. In Compare mode (Figure 14-1), the output compare module can be configured for single-shot or continuous pulse generation. It can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. 2. Configure the OCx output for one of the available Peripheral Pin Select pins. Calculate the required values for the OCxR and (for Double Compare modes) OCxRS Duty Cycle registers: a) Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. b) Calculate time to the rising edge of the output pulse relative to the timer start value (0000h). c) Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 7. 8. Write the rising edge value to OCxR and the falling edge value to OCxRS. Set the Timer Period register, PRy, to a value equal to or greater than the value in OCxRS. Set the OCM<2:0> bits for the appropriate compare operation (= 0xx). For Trigger mode operations, set OCTRIG to enable Trigger mode. Set or clear TRIGMODE to configure trigger operation and TRIGSTAT to select a hardware or software trigger. For Synchronous mode, clear OCTRIG. Set the SYNCSEL<4:0> bits to configure the trigger or synchronization source. If free-running timer operation is required, set the SYNCSEL bits to `00000' (no sync/trigger source). Select the time base source with the OCTSEL<2:0> bits. If necessary, set the TON bits for the selected timer, which enables the compare time base to count. Synchronous mode operation starts as soon as the time base is enabled; Trigger mode operation starts after a trigger source event occurs. DS39969B-page 202 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. Set the OC32 bits for both registers (OCyCON2<8>) and (OCxCON2<8>). Enable the even numbered module first to ensure the modules will start functioning in unison. Clear the OCTRIG bit of the even module (OCyCON2), so the module will run in Synchronous mode. Configure the desired output and Fault settings for OCy. Force the output pin for OCx to the output state by clearing the OCTRIS bit. If Trigger mode operation is required, configure the trigger options in OCx by using the OCTRIG (OCxCON2<7>), TRIGMODE (OCxCON1<3>) and SYNCSEL (OCxCON2<4:0>) bits. Configure the desired Compare or PWM mode of operation (OCM<2:0>) for OCy first, then for OCx. 14.3 Pulse-Width Modulation (PWM) Mode 2. In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). To configure the output compare module for PWM operation: 1. 2. 3. 4. Configure the OCx output for one of the available Peripheral Pin Select pins. Calculate the desired duty cycles and load them into the OCxR register. Calculate the desired period and load it into the OCxRS register. Select the current OCx as the synchronization source by writing 0x1F to the SYNCSEL<4:0> bits (OCxCON2<4:0>) and `0' to the OCTRIG bit (OCxCON2<7>). Select a clock source by writing to the OCTSEL<2:0> bits (OCxCON<12:10>). Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization. Select the desired PWM mode in the OCM<2:0> bits (OCxCON1<2:0>). Appropriate Fault inputs may be enabled by using the ENFLT<2:0> bits as described in Register 14-1. If a timer is selected as a clock source, set the selected timer prescale value. The selected timer's prescaler output is used as the clock input for the OCx timer, and not the selected timer output. Note: This peripheral contains input and output functions that may need to be configured by the Peripheral Pin Select. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. 3. 4. 5. 6. Depending on the output mode selected, the module holds the OCx pin in its default state and forces a transition to the opposite state when OCxR matches the timer. In Double Compare modes, OCx is forced back to its default state when a match with OCxRS occurs. The OCxIF interrupt flag is set after an OCxR match in Single Compare modes and after each OCxRS match in Double Compare modes. Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated. 5. 6. 7. 8. 9. 2010 Microchip Technology Inc. DS39969B-page 203 PIC24FJ256DA210 FAMILY FIGURE 14-2: OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCxCON2 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxR and DCB<1:0> Rollover/Reset OCxR and DCB<1:0> Buffers Comparator OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT<2:0> OCFLT<2:0> DCB<1:0> OCx Pin(1) OC Clock Sources Clock Select Increment Match Event OC Output and Rollover Fault Logic OCFA/OCFB(2) Match Event OCxTMR Reset Match Event Comparator Trigger and Sync Sources Trigger and Sync Logic OCxRS Buffer Rollover/Reset OCxRS OCx Interrupt Reset Note 1: 2: The OCx outputs must be assigned to an available RPn pin before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. The OCFA/OCFB fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. 14.3.1 PWM PERIOD The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation 14-1. EQUATION 14-1: CALCULATING THE PWM PERIOD(1) PWM Period = [(PRy) + 1 * TCY * (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled. Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles. DS39969B-page 204 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 14.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. Some important boundary parameters of the PWM duty cycle include: * If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty cycle). * If OCxRS is greater than PRy, the pin will remain high (100% duty cycle). See Example 14-1 for PWM mode timing details. Table 14-1 and Table 14-2 show example PWM frequencies and resolutions for a device operating at 4 MIPS and 10 MIPS, respectively. EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1) log10 Maximum PWM Resolution (bits) = ( FPWM * (Timer Prescale Value) ) log10(2) FCY bits Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. EXAMPLE 14-1: 1. PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 ms PWM Period = (PR2 + 1) * TCY * (Timer2 Prescale Value) 19.2 ms = PR2 + 1) * 62.5 ns * 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate: PWM Resolution = log10 (FCY/FPWM)/log102) bits = (log10 (16 MHz/52.08 kHz)/log102) bits = 8.3 bits Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1) 7.6 Hz 8 FFFFh 16 61 Hz 1 FFFFh 16 122 Hz 1 7FFFh 15 977 Hz 1 0FFFh 12 3.9 kHz 1 03FFh 10 31.3 kHz 1 007Fh 7 125 kHz 1 001Fh 5 PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1) 30.5 Hz 8 FFFFh 16 244 Hz 1 FFFFh 16 488 Hz 1 7FFFh 15 3.9 kHz 1 0FFFh 12 15.6 kHz 1 03FFh 10 125 kHz 1 007Fh 7 500 kHz 1 001Fh 5 PWM Frequency Timer Prescaler Ratio Period Register Value Resolution (bits) Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2010 Microchip Technology Inc. DS39969B-page 205 PIC24FJ256DA210 FAMILY REGISTER 14-1: U-0 -- bit 15 R/W-0 ENFLT0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (2) OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 -- R/W-0 OCSIDL R/W-0 OCTSEL2 R/W-0 OCTSEL1 R/W-0 OCTSEL0 R/W-0 ENFLT2 (2) R/W-0 ENFLT1(2) bit 8 R/W-0, HSC OCFLT2 (2) R/W-0, HSC OCFLT1 (2) R/W-0, HSC OCFLT0 (2) R/W-0 TRIGMODE R/W-0 OCM2 (1) R/W-0 OCM1 (1) R/W-0 OCM0(1) bit 0 Unimplemented: Read as `0' OCSIDL: Stop Output Compare x in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode OCTSEL<2:0>: Output Compare x Timer Select bits 111 = Peripheral clock (FCY) 110 = Reserved 101 = Reserved 100 = Timer1 clock (only synchronous clock is supported) 011 = Timer5 clock 010 = Timer4 clock 001 = Timer3 clock 000 = Timer2 clock ENFLT2: Fault Input 2 Enable bit(2) 1 = Fault 2 (Comparator 1/2/3 out) is enabled(3) 0 = Fault 2 is disabled ENFLT1: Fault Input 1 Enable bit(2) 1 = Fault 1 (OCFB pin) is enabled(4) 0 = Fault 1 is disabled ENFLT0: Fault Input 0 Enable bit(2) 1 = Fault 0 (OCFA pin) is enabled(4) 0 = Fault 0 is disabled OCFLT2: PWM Fault 2 (Comparator 1/2/3) Condition Status bit(2,3) 1 = PWM Fault 2 has occurred 0 = No PWM Fault 2 has occurred OCFLT1: PWM Fault 1 (OCFB pin) Condition Status bit(2,4) 1 = PWM Fault 1 has occurred 0 = No PWM Fault 1 has occurred OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit(2,4) 1 = PWM Fault 0 has occurred 0 = No PWM Fault 0 has occurred The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4 "Peripheral Pin Select (PPS)". The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6 channels; Comparator 3 output controls the OC7-OC9 channels. The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section 10.4 "Peripheral Pin Select (PPS)". bit 12-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 Note 1: 2: 3: 4: DS39969B-page 206 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 14-1: bit 3 OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx(2) 110 = Edge-Aligned PWM Mode on OCx(2) 101 = Double Compare Continuous Pulse mode: Initialize the OCx pin low, the toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initialize the OCx pin low, toggle the OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin 010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces the OCx pin low 001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces the OCx pin high 000 = Output compare channel is disabled The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4 "Peripheral Pin Select (PPS)". The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6 channels; Comparator 3 output controls the OC7-OC9 channels. The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section 10.4 "Peripheral Pin Select (PPS)". bit 2-0 Note 1: 2: 3: 4: 2010 Microchip Technology Inc. DS39969B-page 207 PIC24FJ256DA210 FAMILY REGISTER 14-2: R/W-0 FLTMD bit 15 R/W-0 OCTRIG bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 HS TRIGSTAT R/W-0 OCTRIS R/W-0 SYNCSEL4 R/W-1 SYNCSEL3 R/W-1 SYNCSEL2 R/W-0 SYNCSEL1 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 FLTTRIEN R/W-0 OCINV U-0 -- R/W-0 FLTOUT R/W-0 DCB1 (3) R/W-0 DCB0 (3) R/W-0 OC32 bit 8 R/W-0 SYNCSEL0 bit 0 FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is cleared in software 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault FLTTRIEN: Fault Output State Select bit 1 = Pin is forced to an output on a Fault condition 0 = Pin I/O condition is unaffected by a Fault OCINV: OCMP Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted Unimplemented: Read as `0' DCB<11:0>: PWM Duty Cycle Least Significant bits(3) 11 = Delay OCx falling edge by 3/4 of the instruction cycle 10 = Delay OCx falling edge by 1/2 of the instruction cycle 01 = Delay OCx falling edge by 1/4 of the instruction cycle 00 = OCx falling edge occurs at the start of the instruction cycle OC32: Cascade Two OC Modules Enable bit (32-bit operation) 1 = Cascade module operation enabled 0 = Cascade module operation disabled OCTRIG: OCx Trigger/Sync Select bit 1 = Trigger OCx from the source designated by the SYNCSELx bits 0 = Synchronize OCx with the source designated by the SYNCSELx bits TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear OCTRIS: OCx Output Pin Direction Select bit 1 = OCx pin is tri-stated 0 = Output compare peripheral x is connected to an OCx pin Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources. The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110). bit 14 bit 13 bit 12 bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5 Note 1: 2: 3: DS39969B-page 208 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 14-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 1000x = Reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2 01011 = Timer1 01010 = Input Capture 5(2) 01001 = Output Compare 9(1) 01000 = Output Compare 8(1) 00111 = Output Compare 7(1) 00110 = Output Compare 6(1) 00101 = Output Compare 5(1) 00100 = Output Compare 4(1) 00011 = Output Compare 3(1) 00010 = Output Compare 2(1) 00001 = Output Compare 1(1) 00000 = Not synchronized to any other module Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources. The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110). Note 1: 2: 3: 2010 Microchip Technology Inc. DS39969B-page 209 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 210 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 15.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 23. "Serial Peripheral Interface (SPI)" (DS39699). The information in this data sheet supersedes the information in the FRM. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. The SPI serial interface consists of four pins: * * * * SDIx: Serial Data Input SDOx: Serial Data Output SCKx: Shift Clock Input or Output SSx: Active-Low Slave Select or Frame Synchronization I/O Pulse The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with the SPI and SIOP Motorola(R) interfaces. All devices of the PIC24FJ256DA210 family include three SPI modules. The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer. In Enhanced Buffer mode, data is shifted through an 8-level FIFO buffer. Note: Do not perform read-modify-write operations (such as bit-oriented instructions) on the SPIxBUF register in either Standard or Enhanced Buffer mode. The SPI module can be configured to operate using 2, 3 or 4 pins. In the 3-pin mode, SSx is not used. In the 2-pin mode, both SDOx and SSx are not used. Block diagrams of the module in Standard and Enhanced modes are shown in Figure 15-1 and Figure 15-2. Note: In this section, the SPI modules are referred to together as SPIx or separately as SPI1, SPI2 or SPI3. Special Function Registers will follow a similar notation. For example, SPIxCON1 and SPIxCON2 refer to the control registers for any of the 3 SPI modules. 2010 Microchip Technology Inc. DS39969B-page 211 PIC24FJ256DA210 FAMILY To set up the SPI module for the Standard Master mode of operation: 1. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. To set up the SPI module for the Standard Slave mode of operation: 1. 2. Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit (SPIxCON1<8>) is set, then the SSEN bit (SPIxCON1<7>) must be set to enable the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 2. 3. 3. 4. 5. 4. 5. 6. 7. FIGURE 15-1: SCKx SPIx MODULE BLOCK DIAGRAM (STANDARD MODE) 1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler FCY SSx/FSYNCx SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock SDOx SDIx bit 0 SPIxSR Transfer Transfer SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus DS39969B-page 212 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation: 1. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 2. Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 2. 3. 3. 4. 5. 6. 4. 5. 6. 7. 8. FIGURE 15-2: SCKx SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE) 1:1 to 1:8 Secondary Prescaler Sync Control Control Clock Shift Control Select Edge 1:1/4/16/64 Primary Prescaler FCY SSx/FSYNCx SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock SPIxSR SDOx SDIx bit 0 Transfer Transfer 8-Level FIFO Receive Buffer 8-Level FIFO Transmit Buffer SPIXBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus 2010 Microchip Technology Inc. DS39969B-page 213 PIC24FJ256DA210 FAMILY REGISTER 15-1: R/W-0 SPIEN(1) bit 15 R-0, HSC SRMPT bit 7 Legend: R = Readable bit -n = Value at POR C = Clearable bit W = Writable bit `1' = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0, HS SPIROV R-0, HSC SRXMPT R/W-0 SISEL2 R/W-0 SISEL1 R/W-0 SISEL0 R-0, HSC SPITBF SPIxSTAT: SPIx STATUS AND CONTROL REGISTER U-0 -- R/W-0 SPISIDL U-0 -- U-0 -- R-0, HSC SPIBEC2 R-0, HSC SPIBEC1 R-0, HSC SPIBEC0 bit 8 R-0, HSC SPIRBF bit 0 HSC = Hardware Settable/Clearable bit bit 15 SPIEN: SPIx Enable bit(1) 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module Unimplemented: Read as `0' SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPI transfers pending. Slave mode: Number of SPI transfers unread. SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and ready to send or receive 0 = SPIx Shift register is not empty SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded (The user software has not read the previous data in the SPIxBUF register.) 0 = No overflow has occurred SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when the last bit is shifted into SPIxSR; as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot 011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit set) 010 = Interrupt when the SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in the receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT bit set) If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 14 bit 13 bit 12-11 bit 10-8 bit 7 bit 6 bit 5 bit 4-2 Note 1: DS39969B-page 214 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 15-1: bit 1 SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR. In Enhanced Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty In Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from the SPIxSR to the buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 215 PIC24FJ256DA210 FAMILY REGISTER 15-2: U-0 -- bit 15 R/W-0 SSEN(4) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CKP R/W-0 MSTEN R/W-0 SPRE2 R/W-0 SPRE1 R/W-0 SPRE0 R/W-0 PPRE1 SPIXCON1: SPIx CONTROL REGISTER 1 U-0 -- U-0 -- R/W-0 DISSCK (1) R/W-0 DISSDO (2) R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(3) bit 8 R/W-0 PPRE0 bit 0 Unimplemented: Read as `0' DISSCK: Disable SCKx Pin bit (SPI Master modes only)(1) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled DISSDO: Disable SDOx Pin bit(2) 1 = SDOx pin is not used by the module; pin functions as I/O 0 = SDOx pin is controlled by the module MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at the end of data output time 0 = Input data sampled at the middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. CKE: SPIx Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) SSEN: Slave Select Enable (Slave mode) bit(4) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by the module; pin is controlled by the port function CKP: Clock Polarity Select bit 1 = Idle state for the clock is a high level; active state is a low level 0 = Idle state for the clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1). If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 Note 1: 2: 3: 4: DS39969B-page 216 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 15-2: bit 4-2 SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1). If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 1-0 Note 1: 2: 3: 4: 2010 Microchip Technology Inc. DS39969B-page 217 PIC24FJ256DA210 FAMILY REGISTER 15-3: R/W-0 FRMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SPIFE SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 SPIFPOL U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 SPIBEN bit 0 R/W-0 SPIFSD FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled 0 = Framed SPIx support is disabled SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low Unimplemented: Read as `0' SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with the first bit clock 0 = Frame sync pulse precedes the first bit clock SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced buffer is enabled 0 = Enhanced buffer is disabled (Legacy mode) bit 14 bit 13 bit 12-2 bit 1 bit 0 DS39969B-page 218 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) Processor 1 (SPI Master) Processor 2 (SPI Slave) SDOx Serial Receive Buffer (SPIxRXB) SDIx Serial Receive Buffer (SPIxRXB)(2) Shift Register (SPIxSR) MSb LSb SDIx SDOx MSb Shift Register (SPIxSR)(2) LSb Serial Transmit Buffer (SPIxTXB) Serial Transmit Buffer (SPIxTXB)(2) Serial Clock SPIx Buffer (SPIxBUF)(2) SCKx SCKx SSx(1) SPIx Buffer (SPIxBUF)(2) MSTEN (SPIxCON1<5>) = 1) Note 1: 2: SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 Using the SSx pin in Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 15-4: SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) Processor 2 (SPI Enhanced Buffer Slave) SDIx SDOx MSb Processor 1 (SPI Enhanced Buffer Master) SDOx SDIx LSb Shift Register (SPIxSR) MSb Shift Register (SPIxSR) LSb 8-Level FIFO Buffer 8-Level FIFO Buffer SPIx Buffer (SPIxBUF)(2) SCKx SSx Serial Clock SCKx SSx(1) SPIx Buffer (SPIxBUF)(2) MSTEN (SPIxCON1<5>) = 1 and SPIBEN (SPIxCON2<0>) = 1 Note 1: 2: Using the SSx pin in Slave mode of operation is optional. SSEN (SPIxCON1<7>) = 1, MSTEN (SPIxCON1<5>) = 0 and SPIBEN (SPIxCON2<0>) = 1 User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. 2010 Microchip Technology Inc. DS39969B-page 219 PIC24FJ256DA210 FAMILY FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Master, Frame Master) SDOx SDIx SCKx SSx Serial Clock SDIx SDOx SCKx SSx Processor 2 Frame Sync Pulse FIGURE 15-6: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24F SPI Master, Frame Slave) SDOx SDIx SCKx SSx Serial Clock SDIx SDOx SCKx SSx Processor 2 Frame Sync Pulse FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Master) SDOx SDIx SCKx SSx Serial Clock SDIx SDOx SCKx SSx Processor 2 Frame Sync. Pulse FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) SDOx SDIx SCKx SSx Serial Clock SDIx SDOx SCKx SSx Processor 2 Frame Sync Pulse DS39969B-page 220 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FSCK = Note 1: FCY Primary Prescaler x Secondary Prescaler Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 15-1: SAMPLE SCKx FREQUENCIES(1,2) FCY = 16 MHz 1:1 Secondary Prescaler Settings 1:1 Invalid 4000 1000 250 4:1 16:1 64:1 FCY = 5 MHz 1:1 5000 1250 313 78 2500 625 156 39 1250 313 78 20 833 208 52 13 625 156 39 10 4:1 16:1 64:1 2:1 8000 2000 500 125 4:1 4000 1000 250 63 6:1 2667 667 167 42 8:1 2000 500 125 31 Primary Prescaler Settings Primary Prescaler Settings Note 1: 2: Based on FCY = FOSC/2; Doze mode and PLL are disabled. SCKx frequencies shown in kHz. 2010 Microchip Technology Inc. DS39969B-page 221 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 222 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 16.0 Note: INTER-INTEGRATED CIRCUITTM (I2CTM) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 24. "Inter-Integrated CircuitTM (I2CTM)" (DS39702). The information in this data sheet supersedes the information in the FRM. 16.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with. Typically, the sequence of events is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Assert a Start condition on SDAx and SCLx. Send the I 2C device address byte to the slave with a write indication. Wait for and verify an Acknowledge from the slave. Send the first data byte (sometimes known as the command) to the slave. Wait for and verify an Acknowledge from the slave. Send the serial memory address low byte to the slave. Repeat steps 4 and 5 until all data bytes are sent. Assert a Repeated Start condition on SDAx and SCLx. Send the device address byte to the slave with a read indication. Wait for and verify an Acknowledge from the slave. Enable master reception to receive serial memory data. Generate an ACK or NACK condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx. The Inter-Integrated CircuitTM (I2CTM) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, display drivers, A/D Converters, etc. The I2C module supports these features: * * * * * * * * * Independent master and slave logic 7-bit and 10-bit device addresses General call address, as defined in the I2C protocol Clock stretching to provide delays for the processor to respond to a slave data request Both 100 kHz and 400 kHz bus specifications Configurable address masking Multi-Master modes to prevent loss of messages in arbitration Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address Automatic SCL A block diagram of the module is shown in Figure 16-1. 2010 Microchip Technology Inc. DS39969B-page 223 PIC24FJ256DA210 FAMILY FIGURE 16-1: I2CTM BLOCK DIAGRAM Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSB SDAx Address Match Read SCLx Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic Write I2CxSTAT Read Write I2CxCON Read Collision Detect Acknowledge Generation Clock Stretching Write I2CxTRN LSB Shift Clock Reload Control Read Write I2CxBRG Read BRG Down Counter TCY/2 DS39969B-page 224 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 16.2 Setting Baud Rate When Operating as a Bus Master 16.3 Slave Address Masking To compute the Baud Rate Generator reload value, use Equation 16-1. The I2CxMSK register (Register 16-3) designates address bit positions as "don't care" for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond whether the corresponding address bit value is a `0' or a `1'. For example, when I2CxMSK is set to `00100000', the slave module will detect both addresses, `0000000' and `0100000'. To enable address masking, the Intelligent Peripheral Management Interface (IPMI) must be disabled by clearing the IPMIEN bit (I2CxCON<11>). Note: As a result of changes in the I2CTM protocol, the addresses in Table 16-2 are reserved and will not be Acknowledged in Slave mode. This includes any address mask settings that include any of these addresses. EQUATION 16-1: FSCL = or: I2CxBRG = COMPUTING BAUD RATE RELOAD VALUE(1,2) FCY I2CxBRG + 1 + FCY FSCL - FCY 10,000,000 ( FCY -1 10,000,000 ) Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 16-1: I2CTM CLOCK RATES(1,2) FCY 16 MHz 8 MHz 4 MHz 16 MHz 8 MHz 4 MHz 2 MHz 16 MHz 8 MHz 4 MHz I2CxBRG Value (Decimal) 157 78 39 37 18 9 4 13 6 3 (Hexadecimal) 9D 4E 27 25 12 9 4 D 6 3 Actual FSCL 100 kHz 100 kHz 99 kHz 404 kHz 404 kHz 385 kHz 385 kHz 1.026 MHz 1.026 MHz 0.909 MHz Required System FSCL 100 kHz 100 kHz 100 kHz 400 kHz 400 kHz 400 kHz 400 kHz 1 MHz 1 MHz 1 MHz Note 1: 2: Based on FCY = FOSC/2; Doze mode and PLL are disabled. These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 16-2: Slave Address 0000 000 0000 000 0000 001 0000 01x 0000 1xx 1111 0xx 1111 Note 1: 2: 3: I2CTM RESERVED ADDRESSES(1) R/W Bit 0 1 x x x x General Call Address Start Byte CBus Address Reserved HS Mode Master Code 10-Bit Slave Upper Byte(3) (2) Description 1xx x Reserved The address bits listed here will never cause an address match, independent of address mask settings. The address will be Acknowledged only if GCEN = 1. A match on this address can only occur on the upper byte in 10-Bit Addressing mode. 2010 Microchip Technology Inc. DS39969B-page 225 PIC24FJ256DA210 FAMILY REGISTER 16-1: R/W-0 I2CEN bit 15 R/W-0 GCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 STREN R/W-0 ACKDT R/W-0, HC ACKEN R/W-0, HC RCEN R/W-0, HC PEN R/W-0, HC RSEN I2CxCON: I2Cx CONTROL REGISTER U-0 -- R/W-0 I2CSIDL R/W-1, HC SCLREL R/W-0 IPMIEN R/W-0 A10M R/W-0 DISSLW R/W-0 SMEN bit 8 R/W-0, HC SEN bit 0 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2CTM pins are controlled by port functions Unimplemented: Read as `0' I2CSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write `0' to initiate stretch and write `1' to release clock). Hardware is clear at the beginning of slave transmission. Hardware is clear at the end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write `1' to release clock). Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses are Acknowledged 0 = IPMI mode is disabled A10M: 10-Bit Slave Addressing bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specifications 0 = Disables the SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 DS39969B-page 226 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 16-1: bit 5 I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) ACKDT: Acknowledge Data bit (when operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master. Applicable during master receive.) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit. Hardware is clear at the end of the master Acknowledge sequence. 0 = Acknowledge sequence is not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive data byte. 0 = Receive sequence is not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on the SDAx and SCLx pins. Hardware is clear at the end of the master Stop sequence. 0 = Stop condition is not in progress RSEN: Repeated Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Repeated Start condition on the SDAx and SCLx pins. Hardware is clear at the end of the master Repeated Start sequence 0 = Repeated Start condition is not in progress SEN: Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at end of the master Start sequence. 0 = Start condition is not in progress bit 4 bit 3 bit 2 bit 1 bit 0 2010 Microchip Technology Inc. DS39969B-page 227 PIC24FJ256DA210 FAMILY REGISTER 16-2: R-0, HSC ACKSTAT bit 15 R/C-0, HS IWCOL bit 7 Legend: R = Readable bit -n = Value at POR C = Clearable bit W = Writable bit `1' = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0, HS I2COV R-0, HSC D/A R/C-0, HSC P R/C-0, HSC S R-0, HSC R/W R-0, HSC RBF I2CxSTAT: I2Cx STATUS REGISTER U-0 -- U-0 -- U-0 -- R/C-0, HS BCL R-0, HSC GCSTAT R-0, HSC ADD10 bit 8 R-0, HSC TBF bit 0 R-0, HSC TRSTAT HSC = Hardware Settable/Clearable bit bit 15 ACKSTAT: Acknowledge Status bit 1 = NACK was detected last 0 = ACK was detected last Hardware is set or clear at the end of Acknowledge. TRSTAT: Transmit Status bit (When operating as I2CTM master. Applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at the beginning of master transmission; hardware is clear at the end of slave Acknowledge. Unimplemented: Read as `0' BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware is set at the detection of a bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when the address matches the general call address; hardware is clear at Stop detection. ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at the match of the 2nd byte of the matched 10-bit address; hardware is clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at an occurrence of write to I2CxTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at the device address match. Hardware is set after a transmission finishes or by reception of a slave byte. bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 DS39969B-page 228 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 16-2: bit 4 I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware is set or clear after the reception of an I 2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with the received byte; hardware is clear when the software reads I2CxRCV. TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN; hardware is clear at the completion of data transmission. bit 3 bit 2 bit 1 bit 0 2010 Microchip Technology Inc. DS39969B-page 229 PIC24FJ256DA210 FAMILY REGISTER 16-3: U-0 -- bit 15 R/W-0 AMSK7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 AMSK6 R/W-0 AMSK5 R/W-0 AMSK4 R/W-0 AMSK3 R/W-0 AMSK2 R/W-0 AMSK1 I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 AMSK9 R/W-0 AMSK8 bit 8 R/W-0 AMSK0 bit 0 Unimplemented: Read as `0' AMSK<9:0>: Mask for Address Bit x Select bits 1 = Enable masking for bit x of the incoming message address; bit match is not required in this position 0 = Disable masking for bit x; bit match is required in this position DS39969B-page 230 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 17.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 21. "UART" (DS39708). The information in this data sheet supersedes the information in the FRM. * Fully Integrated Baud Rate Generator with 16-Bit Prescaler * Baud Rates Ranging from 15 bps to 1 Mbps at 16 MIPS * 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer * 4-Deep FIFO Receive Data Buffer * Parity, Framing and Buffer Overrun Error Detection * Support for 9-bit mode with Address Detect (9th bit = 1) * Transmit and Receive Interrupts * Loopback mode for Diagnostic Support * Support for Sync and Break Characters * Supports Automatic Baud Rate Detection * IrDA(R) Encoder and Decoder Logic * 16x Baud Clock Output for IrDA Support A simplified block diagram of the UART is shown in Figure 17-1. The UART module consists of these key important hardware elements: * Baud Rate Generator * Asynchronous Transmitter * Asynchronous Receiver Note: The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family. The UART is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal computers, LIN/J2602, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins, and also includes an IrDA(R) encoder and decoder. The primary features of the UART module are: * Full-Duplex, 8 or 9-Bit data transmission through the UxTX and UxRX pins * Even, Odd or No Parity options (for 8-bit data) * One or two Stop bits * Hardware Flow Control option with the UxCTS and UxRTS pins FIGURE 17-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) Hardware Flow Control UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX Note: The UART inputs and outputs must all be assigned to available RPn/RPIn pins before use. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. 2010 Microchip Technology Inc. DS39969B-page 231 PIC24FJ256DA210 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated, 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate with BRGH = 0. The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 17-2 shows the formula for computation of the baud rate with BRGH = 1. EQUATION 17-2: EQUATION 17-1: UART BAUD RATE WITH BRGH = 0(1,2) UART BAUD RATE WITH BRGH = 1(1,2) FCY 4 * (UxBRG + 1) FCY 4 * Baud Rate -1 FCY Baud Rate = 16 * (UxBRG + 1) UxBRG = Note 1: 2: FCY 16 * Baud Rate -1 Note 1: 2: Baud Rate = UxBRG = FCY denotes the instruction cycle clock frequency (FOSC/2). Based on FCY = FOSC/2; Doze mode and PLL are disabled. FCY denotes the instruction cycle clock frequency. Based on FCY = FOSC/2; Doze mode and PLL are disabled. Example 17-1 shows the calculation of the baud rate error for the following conditions: * FCY = 4 MHz * Desired Baud Rate = 9600 The maximum baud rate (BRGH = 1) possible is FCY/4 (for UxBRG = 0) and the minimum baud rate possible is FCY/(4 * 65536). Writing a new value to the UxBRG register causes the BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. EXAMPLE 17-1: Desired Baud Rate BRGx BRGx BRGx BAUD RATE ERROR CALCULATION (BRGH = 0)(1) = FCY/(16 (BRGx + 1)) = ((FCY/Desired Baud Rate)/16) - 1 = ((4000000/9600)/16) - 1 = 25 Solving for BRGx Value: Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600)/9600 Based on FCY = FOSC/2; Doze mode and PLL are disabled. Note: DS39969B-page 232 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 17.2 1. Transmitting in 8-Bit Data Mode 17.5 1. 2. 3. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write a data byte to the lower byte of UxTXREG word. The value will be immediately transferred to the Transmit Shift Register (TSR) and the serial bit stream will start shifting out with the next rising edge of the baud clock. Alternately, the data byte may be transferred while UTXEN = 0 and then the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. A transmit interrupt will be generated as per interrupt control bit, UTXISELx. Receiving in 8-Bit or 9-Bit Data Mode 4. 5. Set up the UART (as described in Section 17.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, URXISELx. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read UxRXREG. The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values. 17.6 Operation of UxCTS and UxRTS Control Pins 17.3 1. 2. 3. 4. 5. Transmitting in 9-Bit Data Mode 6. Set up the UART (as described in Section 17.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write UxTXREG as a 16-bit value only. A word write to UxTXREG triggers the transfer of the 9-bit data to the TSR. The serial bit stream will start shifting out with the first rising edge of the baud clock. A transmit interrupt will be generated as per the setting of control bit, UTXISELx. UARTx Clear to Send (UxCTS) and Request to Send (UxRTS) are the two hardware controlled pins that are associated with the UART module. These two pins allow the UART to operate in Simplex and Flow Control mode. They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the UxMODE register configure these pins. 17.7 Infrared Support The UART module provides two types of infrared UART support: one is the IrDA clock output to support an external IrDA encoder and decoder device (legacy module support), and the other is the full implementation of the IrDA encoder and decoder. Note that because the IrDA modes require a 16x baud clock, they will only work when the BRGH bit (UxMODE<3>) is `0'. 17.7.1 17.4 Break and Sync Transmit Sequence IrDA CLOCK OUTPUT FOR EXTERNAL IrDA SUPPORT The following sequence will send a message frame header, made up of a Break, followed by an auto-baud Sync byte. 1. 2. 3. 4. 5. Configure the UART for the desired mode. Set UTXEN and UTXBRK to set up the Break character. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). Write `55h' to UxTXREG; this loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. With UEN<1:0> = 11, the BCLKx pin will output the 16x baud clock if the UART module is enabled. It can be used to support the IrDA codec chip. 17.7.2 BUILT-IN IrDA ENCODER AND DECODER The UART has full implementation of the IrDA encoder and decoder as part of the UART module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE<12>). When enabled (IREN = 1), the receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the infrared transmitter. 2010 Microchip Technology Inc. DS39969B-page 233 PIC24FJ256DA210 FAMILY REGISTER 17-1: R/W-0 UARTEN(1) bit 15 R/W-0, HC WAKE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 LPBACK R/W-0, HC ABAUD R/W-0 RXINV R/W-0 BRGH R/W-0 PDSEL1 R/W-0 PDSEL0 -- UxMODE: UARTx MODE REGISTER U-0 R/W-0 USIDL R/W-0 IREN(2) R/W-0 RTSMD U-0 -- R/W-0 UEN1 R/W-0 UEN0 bit 8 R/W-0 STSEL bit 0 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal Unimplemented: Read as `0' USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode IREN: IrDA(R) Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode Unimplemented: Read as `0' UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by port latches WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. This feature is only available for the 16x BRG mode (BRGH = 0). bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 Note 1: 2: DS39969B-page 234 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 17-1: bit 4 UxMODE: UARTx MODE REGISTER (CONTINUED) RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' BRGH: High Baud Rate Enable bit 1 = High-Speed mode (4 BRG clock cycles per bit) 0 = Standard-Speed mode (16 BRG clock cycles per bit) PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. This feature is only available for the 16x BRG mode (BRGH = 0). bit 3 bit 2-1 bit 0 Note 1: 2: 2010 Microchip Technology Inc. DS39969B-page 235 PIC24FJ256DA210 FAMILY REGISTER 17-2: R/W-0 UTXISEL1 bit 15 R/W-0 URXISEL1 bit 7 Legend: R = Readable bit -n = Value at POR HS = Hardware Settable bit bit 15,13 C = Clearable bit W = Writable bit `1' = Bit is set HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 URXISEL0 R/W-0 ADDEN R-1, HSC RIDLE R-0, HSC PERR R-0, HSC FERR R/C-0, HS OERR UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 UTXISEL0 U-0 -- R/W-0 HC UTXBRK R/W-0 UTXEN(2) R-0, HSC UTXBF R-1, HSC TRMT bit 8 R-0, HSC URXDA bit 0 (1) R/W-0 UTXINV UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) UTXINV: IrDA(R) Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX is Idle `0' 0 = UxTX is Idle `1' IREN = 1: 1 = UxTX is Idle `1' 0 = UxTX is Idle `0' Unimplemented: Read as `0' UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed UTXEN: Transmit Enable bit(2) 1 = Transmit is enabled, UxTX pin controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is controlled by port. UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Value of bit only affects the transmit properties of the module when the IrDA(R) encoder is enabled (IREN = 1). If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 14 bit 12 bit 11 bit 10 bit 9 bit 8 Note 1: 2: DS39969B-page 236 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 17-2: bit 7-6 UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode is disabled RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition); will reset the receiver buffer and the RSR to the empty state URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Value of bit only affects the transmit properties of the module when the IrDA(R) encoder is enabled (IREN = 1). If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 2010 Microchip Technology Inc. DS39969B-page 237 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 238 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.0 UNIVERSAL SERIAL BUS WITH ON-THE-GO SUPPORT (USB OTG) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 27. "USB On-The-Go (OTG)" (DS39721). The information in this data sheet supersedes the information in the FRM. The USB OTG module can function as a USB peripheral device or as a USB host, and may dynamically switch between Device and Host modes under software control. In either mode, the same data paths and Buffer Descriptors (BDs) are used for the transmission and reception of data. In discussing USB operation, this section will use a controller-centric nomenclature for describing the direction of the data transfer between the microcontroller and the USB. RX (Receive) will be used to describe transfers that move data from the USB to the microcontroller and TX (Transmit) will be used to describe transfers that move data from the microcontroller to the USB. Table 18-1 shows the relationship between data direction in this nomenclature and the USB tokens exchanged. Note: PIC24FJ256DA210 family devices contain a full-speed and low-speed compatible, On-The-Go (OTG) USB Serial Interface Engine (SIE). The OTG capability allows the device to act either as a USB peripheral device or as a USB embedded host with limited host capabilities. The OTG capability allows the device to dynamically switch from device to host operation using OTG's Host Negotiation Protocol (HNP). For more details on OTG operation, refer to the "On-The-Go Supplement to the USB 2.0 Specification", published by the USB-IF. For more details on USB operation, refer to the "Universal Serial Bus Specification", v2.0. The USB OTG module offers these features: * USB functionality in Device and Host modes, and OTG capabilities for application-controlled mode switching * Software-selectable module speeds of full speed (12 Mbps) or low speed (1.5 Mbps, available in Host mode only) * Support for all four USB transfer types: control, interrupt, bulk and isochronous * 16 bidirectional endpoints for a total of 32 unique endpoints * DMA interface for data RAM access * Queues up to sixteen unique endpoint transfers without servicing * Integrated, on-chip USB transceiver with support for off-chip transceivers via a digital interface * Integrated VBUS generation with on-chip comparators and boost generation, and support of external VBUS comparators and regulators through a digital interface * Configurations for on-chip bus pull-up and pull-down resistors A simplified block diagram of the USB OTG module is shown in Figure 18-1. TABLE 18-1: CONTROLLER-CENTRIC DATA DIRECTION FOR USB HOST OR TARGET Direction RX OUT or SETUP IN TX IN OUT or SETUP USB Mode Device Host This chapter presents the most basic operations needed to implement USB OTG functionality in an application. A complete and detailed discussion of the USB protocol and its OTG supplement are beyond the scope of this data sheet. It is assumed that the user already has a basic understanding of USB architecture and the latest version of the protocol. Not all steps for proper USB operation (such as device enumeration) are presented here. It is recommended that application developers use an appropriate device driver to implement all of the necessary features. Microchip provides a number of application-specific resources, such as USB firmware and driver support. Refer to www.microchip.com/usb for the latest firmware and driver support. 2010 Microchip Technology Inc. DS39969B-page 239 PIC24FJ256DA210 FAMILY FIGURE 18-1: USB OTG MODULE BLOCK DIAGRAM Full-Speed Pull-up Host Pull-Down D+(1) 48 MHz USB Clock Transceiver VUSB D-(1) Host Pull-Down Transceiver Power 3.3V Registers and Control Interface USBID(1) VMIO(1) VPIO(1) DMH(1) DPH(1) DMLN(1) DPLN(1) RCV(1) USBOEN(1) VBUSON(1) External Transceiver Interface USB SIE System RAM SRP Charge VBUS(1) USB Voltage Comparators SRP Discharge VCMPST1/VBUSVLD(1) VCMPST2/SESSVLD(1) SESSEND(1) VBUSST(1) VCPCON(1) VBUS Boost Assist Note 1: Pins are multiplexed with digital I/O and other device features. DS39969B-page 240 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.1 18.1.1 18.1.1.1 Hardware Configuration DEVICE MODE D+ Pull-up Resistor To meet compliance specifications, the USB module (and the D+ or D- pull-up resistor) should not be enabled until the host actively drives VBUS high. One of the 5.5V tolerant I/O pins may be used for this purpose. The application should never source any current onto the 5V VBUS pin of the USB cable. The Dual Power mode with Self-Power Dominance (Figure 18-5) allows the application to use internal power primarily, but switch to power from the USB when no internal power is available. Dual power devices must also meet all of the special requirements for inrush current and Suspend mode current previously described, and must not enable the USB module until VBUS is driven high. PIC24FJ256DA210 family devices have a built-in 1.5 k resistor on the D+ line that is available when the microcontroller is operating in Device mode. This is used to signal an external Host that the device is operating in Full-Speed Device mode. It is engaged by setting the USBEN bit (U1CON<0>). If the OTGEN bit (U1OTGCON<2>) is set, then the D+ pull-up is enabled through the DPPULUP bit (U1OTGCON<7>). Alternatively, an external resistor may be used on D+, as shown in Figure 18-2. FIGURE 18-2: EXTERNAL PULL-UP FOR FULL-SPEED DEVICE MODE Host Controller/HUB FIGURE 18-3: BUS POWER ONLY 100 Attach Sense VBUS VDD PIC(R) MCU VBUS ~5V 3.3V Low IQ Regulator VUSB VUSB VSS 1.5 k D+ D- FIGURE 18-4: VBUS ~5V SELF-POWER ONLY 100 Attach Sense VBUS VDD 18.1.1.2 Power Modes VSELF ~3.3V Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are: * Bus Power Only mode * Self-Power Only mode * Dual Power with Self-Power Dominance Bus Power Only mode (Figure 18-3) is effectively the simplest method. All power for the application is drawn from the USB. To meet the inrush current requirements of the USB 2.0 Specification, the total effective capacitance appearing across VBUS and ground must be no more than 10 F. In the USB Suspend mode, devices must consume no more than 2.5 mA from the 5V VBUS line of the USB cable. During the USB Suspend mode, the D+ or Dpull-up resistor must remain active, which will consume some of the allowed suspend current. In Self-Power Only mode (Figure 18-4), the USB application provides its own power, with very little power being pulled from the USB. Note that an attach indication is added to indicate when the USB has been connected and the host is actively powering VBUS. VUSB 100 k VSS FIGURE 18-5: DUAL POWER EXAMPLE 100 3.3V Attach Sense VBUS VDD VBUS ~5V Low IQ Regulator 100 k VUSB VSS VSELF ~3.3V 2010 Microchip Technology Inc. DS39969B-page 241 PIC24FJ256DA210 FAMILY 18.1.2 18.1.2.1 HOST AND OTG MODES D+ and D- Pull-Down Resistors the microcontroller is running below VBUS, and is not able to source sufficient current, a separate power supply must be provided. When the application is always operating in Host mode, a simple circuit can be used to supply VBUS and regulate current on the bus (Figure 18-6). For OTG operation, it is necessary to be able to turn VBUS on or off as needed, as the microcontroller switches between Device and Host modes. A typical example using an external charge pump is shown in Figure 18-7. PIC24FJ256DA210 family devices have a built-in 15 k pull-down resistor on the D+ and D- lines. These are used in tandem to signal to the bus that the microcontroller is operating in Host mode. They are engaged by setting the HOSTEN bit (U1CON<3>). If the OTGEN bit (U1OTGCON<2>) is set, then these pull-downs are enabled by setting the DPPULDWN and DMPULDWN bits (U1OTGCON<5:4>). 18.1.2.2 Power Configurations In Host mode, as well as Host mode in On-The-Go operation, the USB 2.0 Specification requires that the host application should supply power on VBUS. Since FIGURE 18-6: HOST INTERFACE EXAMPLE +5V Thermal Fuse Polymer PTC 0.1 F, 3.3V A/D Pin 2 k VBUS D+ DID VSS +3.3V +3.3V PIC(R) MCU VDD VUSB 150 F Micro A/B Connector VBUS D+ DID GND 2 k FIGURE 18-7: OTG INTERFACE EXAMPLE VDD MCP1253 GND C+ 1 F CVOUT VIN SELECT SHND PGOOD 10 F I/O I/O PIC(R) MCU Micro A/B Connector 4.7 F VBUS D+ DID GND 40 k VBUS D+ DID VSS DS39969B-page 242 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.1.2.3 VBUS Voltage Generation with External Devices 18.1.3 USING AN EXTERNAL INTERFACE When operating as a USB host, either as an A-device in an OTG configuration or as an embedded host, VBUS must be supplied to the attached device. PIC24FJ256DA210 family devices have an internal VBUS boost assist to help generate the required 5V VBUS from the available voltages on the board. This is comprised of a simple PWM output to control a Switch mode power supply, and built-in comparators to monitor output voltage and limit current. To enable voltage generation: 1. Verify that the USB module is powered (U1PWRC<0> = 1) and that the VBUS discharge is disabled (U1OTGCON<0> = 0). Set the PWM period (U1PWMRRS<7:0>) and duty cycle (U1PWMRRS<15:8>) as required. Select the required polarity of the output signal based on the configuration of the external circuit with the PWMPOL bit (U1PWMCON<9>). Select the desired target voltage using the VBUSCHG bit (U1OTGCON<1>). Enable the PWM counter by setting the CNTEN bit to `1' (U1PWMCON<8>). Enable the PWM module by setting the PWMEN bit (U1PWMCON<15>) to `1'. generation circuit Enable the VBUS (U1OTGCON<3> = 1). Note: This section describes the general process for VBUS voltage generation and control. Please refer to the "PIC24F Family Reference Manual" for additional examples. Some applications may require the USB interface to be isolated from the rest of the system. PIC24FJ256DA210 family devices include a complete interface to communicate with and control an external USB transceiver, including the control of data line pull-ups and pull-downs. The VBUS voltage generation control circuit can also be configured for different VBUS generation topologies. Refer to the "PIC24F Family Reference Manual", Section 27. "USB On-The-Go (OTG)" for information on using the external interface. 18.1.4 CALCULATING TRANSCEIVER POWER REQUIREMENTS 2. 3. 4. 5. 6. 7. The USB transceiver consumes a variable amount of current depending on the characteristic impedance of the USB cable, the length of the cable, the VUSB supply voltage and the actual data patterns moving across the USB cable. Longer cables have larger capacitances and consume more total energy when switching output states. The total transceiver current consumption will be application-specific. Equation 18-1 can help estimate how much current actually may be required in full-speed applications. Refer to the "PIC24F Family Reference Manual", Section 27. "USB On-The-Go (OTG)" for a complete discussion on transceiver power consumption. EQUATION 18-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION IXCVR = 40 mA * VUSB * PZERO * PIN * LCABLE + IPULLUP 3.3V * 5m Legend: VUSB - Voltage applied to the VUSB pin in volts (3.0V to 3.6V). PZERO - Percentage (in decimal) of the IN traffic bits sent by the PIC(R) microcontroller that are a value of `0'. PIN - Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE - Length (in meters) of the USB cable. The USB 2.0 Specification requires that full-speed applications use cables no longer than 5m. IPULLUP - Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB cable. 2010 Microchip Technology Inc. DS39969B-page 243 PIC24FJ256DA210 FAMILY 18.2 USB Buffer Descriptors and the BDT Depending on the endpoint buffering configuration used, there are up to 64 sets of Buffer Descriptors, for a total of 256 bytes. At a minimum, the BDT must be at least 8 bytes long. This is because the USB Specification mandates that every device must have Endpoint 0 with both input and output for initial setup. Endpoint mapping in the BDT is dependent on three variables: * Endpoint number (0 to 15) * Endpoint direction (RX or TX) * Ping-pong settings (U1CNFG1<1:0>) Figure 18-8 illustrates how these variables are used to map endpoints in the BDT. In Host mode, only Endpoint 0 Buffer Descriptors are used. All transfers utilize the Endpoint 0 Buffer Descriptor and Endpoint Control register (U1EP0). For received packets, the attached device's source endpoint is indicated by the value of ENDPT<3:0> in the USB status register (U1STAT<7:4>). For transmitted packet, the attached device's destination endpoint is indicated by the value written to the Token register (U1TOK). Endpoint buffer control is handled through a structure called the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configurations. The BDT can be located in any available, 512-byte aligned block of data RAM. The BDT Pointer (U1BDTP1) contains the upper address byte of the BDT and sets the location of the BDT in RAM. The user must set this pointer to indicate the table's location. The BDT is composed of Buffer Descriptors (BDs) which are used to define and control the actual buffers in the USB RAM space. Each BD consists of two, 16-bit "soft" (non-fixed-address) registers, BDnSTAT and BDnADR, where n represents one of the 64 possible BDs (range of 0 to 63). BDnSTAT is the status register for BDn, while BDnADR specifies the starting address for the buffer associated with BDn. Note: Since BDnADR is a 16-bit register, only the first 64 Kbytes of RAM can be accessed by the USB module. FIGURE 18-8: PPB<1:0> = 00 No Ping-Pong Buffers Total BDT Space: 128 Bytes BDT MAPPING FOR ENDPOINT BUFFERING MODES PPB<1:0> = 01 Ping-Pong Buffer on EP0 OUT Total BDT Space: 132 Bytes EP0 RX Even Descriptor EP0 RX Odd Descriptor EP0 TX Descriptor EP1 RX Descriptor EP1 TX Descriptor EP15 TX Descriptor EP15 TX Descriptor PPB<1:0> = 10 Ping-Pong Buffers on all EPs Total BDT Space: 256 Bytes EP0 RX Even Descriptor EP0 RX Odd Descriptor EP0 TX Even Descriptor EP0 TX Odd Descriptor EP1 RX Even Descriptor EP1 RX Odd Descriptor EP1 TX Even Descriptor EP1 TX Odd Descriptor PPB<1:0> = 11 Ping-Pong Buffers on all other EPs except EP0 Total BDT Space: 248 Bytes EP0 RX Descriptor EP0 TX Descriptor EP1 RX Even Descriptor EP1 RX Odd Descriptor EP1 TX Even Descriptor EP1 TX Odd Descriptor EP0 RX Descriptor EP0 TX Descriptor EP1 RX Descriptor EP1 TX Descriptor EP15 TX Odd Descriptor Note: Memory area is not shown to scale. EP15 TX Odd Descriptor DS39969B-page 244 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. Table 18-2 provides the mapping of BDs to endpoints. This relationship also means that gaps may occur in the BDT if endpoints are not enabled contiguously. This, theoretically, means that the BDs for disabled endpoints could be used as buffer space. In practice, users should avoid using such spaces in the BDT unless a method of validating BD addresses is implemented. corresponding data buffer during this time. Note that the microcontroller core can still read BDnSTAT while the SIE owns the buffer and vice versa. The Buffer Descriptors have a different meaning based on the source of the register update. Register 18-1 and Register 18-2 show the differences in BDnSTAT depending on its current "ownership". When UOWN is set, the user can no longer depend on the values that were written to the BDs. From this point, the USB module updates the BDs as necessary, overwriting the original BD values. The BDnSTAT register is updated by the SIE with the token PID and the transfer count is updated. 18.2.1 BUFFER OWNERSHIP Because the buffers and their BDs are shared between the CPU and the USB module, a simple semaphore mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory. This is done by using the UOWN bit as a semaphore to distinguish which is allowed to update the BD and associated buffers in memory. UOWN is the only bit that is shared between the two configurations of BDnSTAT. When UOWN is clear, the BD entry is "owned" by the microcontroller core. When the UOWN bit is set, the BD entry and the buffer memory are "owned" by the USB peripheral. The core should not modify the BD or its 18.2.2 DMA INTERFACE The USB OTG module uses a dedicated DMA to access both the BDT and the endpoint data buffers. Since part of the address space of the DMA is dedicated to the Buffer Descriptors, a portion of the memory connected to the DMA must comprise a contiguous address space properly mapped for the access by the module. TABLE 18-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 3 (Ping-Pong on all other EPs, except EP0) Out 0 2 (E), 3 (O) 6 (E), 7 (O) 10 (E), 11 (O) In 1 4 (E), 5 (O) 8 (E), 9 (O) 12 (E), 13 (O) Endpoint Mode 0 (No Ping-Pong) Out In 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 Mode 1 (Ping-Pong on EP0 OUT) Out 0 (E), 1 (O) 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 In 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Mode 2 (Ping-Pong on all EPs) Out 0 (E), 1 (O) 4 (E), 5 (O) 8 (E), 9 (O) 12 (E), 13 (O) 16 (E), 17 (O) 20 (E), 21 (O) 24 (E), 25 (O) 28 (E), 29 (O) 32 (E), 33 (O) 36 (E), 37 (O) 40 (E), 41 (O) 44 (E), 45 (O) 48 (E), 49 (O) 52 (E), 53 (O) 56 (E), 57 (O) 60 (E), 61 (O) In 2 (E), 3 (O) 6 (E), 7 (O) 10 (E), 11 (O) 14 (E), 15 (O) 18 (E), 19 (O) 22 (E), 23 (O) 26 (E), 27 (O) 34 (E), 35 (O) 38 (E), 39 (O) 42 (E), 43 (O) 46 (E), 47 (O) 50 (E), 51 (O) 54 (E), 55 (O) 58 (E), 59 (O) 62 (E), 63 (O) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Legend: 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 14 (E), 15 (O) 16 (E), 17 (O) 18 (E), 19 (O) 20 (E), 21 (O) 22 (E), 23 (O) 24 (E), 25 (O) 30 (E), 31 (O) 32 (E), 33 (O) 34 (E), 35 (O) 36 (E), 37 (O) 38 (E), 39 (O) 40 (E), 41 (O) 42 (E), 43 (O) 44 (E), 45 (O) 46 (E), 47 (O) 48 (E), 49 (O) 50 (E), 51 (O) 52 (E), 53 (O) 54 (E), 55 (O) 56 (E), 57 (O) 58 (E), 59 (O) 60 (E), 61 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O) (E) = Even transaction buffer, (O) = Odd transaction buffer 2010 Microchip Technology Inc. DS39969B-page 245 PIC24FJ256DA210 FAMILY REGISTER 18-1: R/W-x UOWN bit 15 R/W-x, HSC BC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x, HSC BC6 R/W-x, HSC BC5 R/W-x, HSC BC4 R/W-x, HSC BC3 R/W-x, HSC BC2 R/W-x, HSC BC1 BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, USB MODE (BD0STAT THROUGH BD63STAT) R/W-x, HSC PID3 R/W-x, HSC PID2 R/W-x, HSC PID1 R/W-x, HSC PID0 R/W-x, HSC BC9 R/W-x, HSC BC8 bit 8 R/W-x, HSC BC0 bit 0 DTS R/W-x UOWN: USB Own bit 1 = The USB module owns the BD and its corresponding buffer; the CPU must not modify the BD or the buffer DTS: Data Toggle Packet bit 1 = Data 1 packet 0 = Data 0 packet PID<3:0>: Packet Identifier bits (written by the USB module) In Device mode: Represents the PID of the received token during the last transfer. In Host mode: Represents the last returned PID or the transfer status indicator. BC<9:0>: Byte Count bits This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. bit 14 bit 13-10 bit 9-0 DS39969B-page 246 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-2: R/W-x UOWN bit 15 R/W-x, HSC BC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set `r' = Reserved bit r = Reserved bit x = Bit is unknown R/W-x, HSC BC6 R/W-x, HSC BC5 R/W-x, HSC BC4 R/W-x, HSC BC3 R/W-x, HSC BC2 R/W-x, HSC BC1 BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU MODE (BD0STAT THROUGH BD63STAT) r-0 Reserved r-0 Reserved R/W-x DTSEN R/W-x BSTALL R/W-x, HSC BC9 R/W-x, HSC BC8 bit 8 R/W-x, HSC BC0 bit 0 (1) R/W-x DTS U = Unimplemented bit, read as `0' UOWN: USB Own bit 0 = The microcontroller core owns the BD and its corresponding buffer; the USB module ignores all other fields in the BD DTS: Data Toggle Packet bit(1) 1 = Data 1 packet 0 = Data 0 packet Reserved: Maintain as `0' DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect sync value will be ignored 0 = No data toggle synchronization is performed BSTALL: Buffer Stall Enable bit 1 = Buffer STALL enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged); corresponding EPSTALL bit will get set on any STALL handshake 0 = Buffer STALL disabled BC<9:0>: Byte Count bits This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. This bit is ignored unless DTSEN = 1. bit 14 bit 13-12 bit 11 bit 10 bit 9-0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 247 PIC24FJ256DA210 FAMILY 18.3 USB Interrupts The USB OTG module has many conditions that can be configured to cause an interrupt. All interrupt sources use the same interrupt vector. Figure 18-9 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts; these are enabled and flagged in the U1IE and U1IR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the U1EIR and U1EIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level. Interrupts may be used to trap routine events in a USB transaction. Figure 18-10 provides some common events within a USB frame and their corresponding interrupts. FIGURE 18-9: USB OTG INTERRUPT FUNNEL Top Level (USB Status) Interrupts STALLIF STALLIE ATTACHIF ATTACHIE RESUMEIF RESUMEIE IDLEIF IDLEIE TRNIF TRNIE Second Level (USB Error) Interrupts BTSEF BTSEE DMAEF DMAEE BTOEF BTOEE DFN8EF DFN8EE CRC16EF CRC16EE CRC5EF (EOFEF) CRC5EE (EOFEE) PIDEF PIDEE SOFIF SOFIE URSTIF (DETACHIF) URSTIE (DETACHIE) Set USB1IF (UERRIF) UERRIE IDIF IDIE T1MSECIF TIMSECIE LSTATEIF LSTATEIE ACTVIF ACTVIE SESVDIF SESVDIE SESENDIF SESENDIE VBUSVDIF VBUSVDIE Top Level (USB OTG) Interrupts DS39969B-page 248 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.3.1 CLEARING USB OTG INTERRUPTS Unlike device level interrupts, the USB OTG interrupt status flags are not freely writable in software. All USB OTG flag bits are implemented as hardware set only bits. Additionally, these bits can only be cleared in software by writing a `1' to their locations (i.e., performing a MOV type instruction). Writing a `0' to a flag bit (i.e., a BCLR instruction) has no effect. Note: Throughout this data sheet, a bit that can only be cleared by writing a `1' to its location is referred to as "Write 1 to clear". In register descriptions, this function is indicated by the descriptor, "K". FIGURE 18-10: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS From Host From Host Data To Host Data SETUP Token From Host IN Token Start-Of-Frame (SOF) SOFIF To Host ACK From Host ACK To Host ACK Set TRNIF Set TRNIF USB Reset URSTIF From Host From Host OUT Token Empty Data Transaction Set TRNIF Transaction Complete RESET Differential Data SOF SETUP DATA STATUS Control Transfer(1) SOF 1 ms Frame Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. 18.4 Device Mode Operation 5. 6. 7. The following section describes how to perform a common Device mode task. In Device mode, USB transfers are performed at the transfer level. The USB module automatically performs the status phase of the transfer. 18.4.1 1. ENABLING DEVICE MODE 8. 9. 2. 3. 4. Reset the Ping-Pong Buffer Pointers by setting, then clearing, the Ping-Pong Buffer Reset bit, PPBRST (U1CON<1>). Disable all interrupts (U1IE and U1EIE = 00h). Clear any existing interrupt flags by writing FFh to U1IR and U1EIR. Verify that VBUS is present (non OTG devices only). Enable the USB module by setting the USBEN bit (U1CON<0>). Set the OTGEN bit (U1OTGCON<2>) to enable OTG operation. Enable the endpoint zero buffer to receive the first setup packet by setting the EPRXEN and EPHSHK bits for Endpoint 0 (U1EP0<3,0> = 1). Power up the USB module by setting the USBPWR bit (U1PWRC<0>). Enable the D+ pull-up resistor to signal an attach by setting DPPULUP bit (U1OTGCON<7>). 2010 Microchip Technology Inc. DS39969B-page 249 PIC24FJ256DA210 FAMILY 18.4.2 1. 2. 3. RECEIVING AN IN TOKEN IN DEVICE MODE 18.5 Host Mode Operation 4. Attach to a USB host and enumerate as described in "Chapter 9 of the USB 2.0 Specification". Create a data buffer and populate it with the data to send to the host. In the appropriate (even or odd) TX BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer. c) Set the UOWN bit of the status register to `1'. When the USB module receives an IN token, it automatically transmits the data in the buffer. Upon completion, the module updates the status register (BDnSTAT) and sets the Transfer Complete Interrupt Flag, TRNIF (U1IR<3>). The following sections describe how to perform common Host mode tasks. In Host mode, USB transfers are invoked explicitly by the host software. The host software is responsible for the Acknowledge portion of the transfer. Also, all transfers are performed using the Endpoint 0 Control register (U1EP0) and Buffer Descriptors. 18.5.1 1. ENABLE HOST MODE AND DISCOVER A CONNECTED DEVICE 18.4.3 1. RECEIVING AN OUT TOKEN IN DEVICE MODE 2. 3. 4. Attach to a USB host and enumerate as described in "Chapter 9 of the USB 2.0 Specification". Create a data buffer with the amount of data you are expecting from the host. In the appropriate (even or odd) TX BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer. c) Set the UOWN bit of the status register to `1'. When the USB module receives an OUT token, it automatically receives the data sent by the host to the buffer. Upon completion, the module updates the status register (BDnSTAT) and sets the Transfer Complete Interrupt Flag, TRNIF (U1IR<3>). Enable Host mode by setting the HOSTEN bit (U1CON<3>). This causes the Host mode control bits in other USB OTG registers to become available. 2. Enable the D+ and D- pull-down resistors by setting the DPPULDWN and DMPULDWN bits (U1OTGCON<5:4>). Disable the D+ and Dpull-up resistors by clearing the DPPULUP and DMPULUP bits (U1OTGCON<7:6>). 3. At this point, SOF generation begins with the SOF counter loaded with 12,000. Eliminate noise on the USB by clearing the SOFEN bit (U1CON<0>) to disable Start-Of-Frame packet generation. 4. Enable the device attached interrupt by setting the ATTACHIE bit (U1IE<6>). 5. Wait for the device attached interrupt (U1IR<6> = 1). This is signaled by the USB device changing the state of D+ or D- from `0' to `1' (SE0 to J state). After it occurs, wait 100 ms for the device power to stabilize. 6. Check the state of the JSTATE and SE0 bits in U1CON. If the JSTATE bit (U1CON<7>) is `0', the connecting device is low speed. If the connecting device is low speed, set the low LSPDEN and LSPD bits (U1ADDR<7> and U1EP0<7>) to enable low-speed operation. 7. Reset the USB device by setting the USBRST bit (U1CON<4>) for at least 50 ms, sending Reset signaling on the bus. After 50 ms, terminate the Reset by clearing USBRST. 8. In order to keep the connected device from going into suspend, enable the SOF packet generation by setting the SOFEN bit. 9. Wait 10 ms for the device to recover from Reset. 10. Perform enumeration as described by "Chapter 9 of the USB 2.0 Specification". DS39969B-page 250 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.5.2 COMPLETE A CONTROL TRANSACTION TO A CONNECTED DEVICE 8. Initialize the current (even or odd) RX or TX (RX for IN, TX for OUT) EP0 BD to transfer the data. a) Write C040h to BD0STAT. This sets the UOWN, configures Data Toggle (DTS) to DATA1 and sets the byte count to the length of the data buffer (64 or 40h in this case). b) Set BD0ADR to the starting address of the data buffer. 9. Write the Token register with the appropriate IN or OUT token to Endpoint 0, the target device's default control pipe (e.g., write 90h to U1TOK for an IN token for a GET DEVICE DESCRIPTOR command). This initiates an IN token on the bus followed by a data packet from the device to the host. When the data packet completes, the BD0STAT is written and a transfer done interrupt is asserted (the TRNIF flag is set). For control transfers with a single packet data phase, this completes the data phase of the setup transaction as referenced in "Chapter 9 of the USB Specification". If more data needs to be transferred, return to step 8. 10. To initiate the status phase of the setup transaction, set up a buffer in memory to receive or send the zero length status phase data packet. 11. Initialize the current (even or odd) TX EP0 BD to transfer the status data: a) Set the BDT buffer address field to the start address of the data buffer. b) Write 8000h to BD0STAT (set UOWN bit, configure DTS to DATA0 and set byte count to 0). 12. Write the Token register with the appropriate IN or OUT token to Endpoint 0, the target device's default control pipe (e.g., write 01h to U1TOK for an OUT token for a GET DEVICE DESCRIPTOR command). This initiates an OUT token on the bus followed by a zero length data packet from the host to the device. When the data packet completes, the BD is updated with the handshake from the device and a transfer done interrupt is asserted (the TRNIF flag is set). This completes the status phase of the setup transaction as described in "Chapter 9 of the USB Specification". Note: Only one control transaction can be performed per frame. 1. 2. 3. 4. 5. 6. 7. Follow the procedure described in Section 18.5.1 "Enable Host Mode and Discover a Connected Device" to discover a device. Set up the Endpoint Control register for bidirectional control transfers by writing 0Dh to U1EP0 (this sets the EPCONDIS, EPTXEN and EPHSHK bits). Place a copy of the device framework setup command in a memory buffer. See "Chapter 9 of the USB 2.0 Specification" for information on the device framework command set. Initialize the Buffer Descriptor (BD) for the current (even or odd) TX EP0 to transfer the eight bytes of command data for a device framework command (i.e., GET DEVICE DESCRIPTOR): a) Set the BD data buffer address (BD0ADR) to the starting address of the 8-byte memory buffer containing the command. b) Write 8008h to BD0STAT (this sets the UOWN bit and sets a byte count of 8). Set the USB device address of the target device in the address register (U1ADDR<6:0>). After a USB bus Reset, the device USB address will be zero. After enumeration, it will be set to another value between 1 and 127. Write D0h to U1TOK; this is a SETUP token to Endpoint 0, the target device's default control pipe. This initiates a SETUP token on the bus, followed by a data packet. The device handshake is returned in the PID field of BD0STAT after the packets are complete. When the USB module updates BD0STAT, a transfer done interrupt is asserted (the TRNIF flag is set). This completes the setup phase of the setup transaction as referenced in "Chapter 9 of the USB Specification". To initiate the data phase of the setup transaction (i.e., get the data for the GET DEVICE DESCRIPTOR command), set up a buffer in memory to store the received data. 2010 Microchip Technology Inc. DS39969B-page 251 PIC24FJ256DA210 FAMILY 18.5.3 1. SEND A FULL-SPEED BULK DATA TRANSFER TO A TARGET DEVICE 18.6 18.6.1 OTG Operation SESSION REQUEST PROTOCOL (SRP) 2. 3. 4. 5. 6. 7. Follow the procedure described in Section 18.5.1 "Enable Host Mode and Discover a Connected Device" and Section 18.5.2 "Complete a Control Transaction to a Connected Device" to discover and configure a device. To enable transmit and receive transfers with handshaking enabled, write 1Dh to U1EP0. If the target device is a low-speed device, also set the LSPD (U1EP0<7>) bit. If you want the hardware to automatically retry indefinitely if the target device asserts a NAK on the transfer, clear the Retry Disable bit, RETRYDIS (U1EP0<6>). Set up the BD for the current (even or odd) TX EP0 to transfer up to 64 bytes. Set the USB device address of the target device in the address register (U1ADDR<6:0>). Write an OUT token to the desired endpoint to U1TOK. This triggers the module's transmit state machines to begin transmitting the token and the data. Wait for the Transfer Done Interrupt Flag, TRNIF. This indicates that the BD has been released back to the microprocessor and the transfer has completed. If the retry disable bit is set, the handshake (ACK, NAK, STALL or ERROR (0Fh)) is returned in the BD PID field. If a STALL interrupt occurs, the pending packet must be dequeued and the error condition in the target device cleared. If a detach interrupt occurs (SE0 for more than 2.5 s), then the target has detached (U1IR<0> is set). Once the transfer done interrupt occurs (TRNIF is set), the BD can be examined and the next data packet queued by returning to step 2. Note: USB speed, transceiver and pull-ups should only be configured during the module setup phase. It is not recommended to change these settings while the module is enabled. An OTG A-device may decide to power down the VBUS supply when it is not using the USB link through the Session Request Protocol (SRP). Software may do this by clearing VBUSON (U1OTGCON<3>). When the VBUS supply is powered down, the A-device is said to have ended a USB session. An OTG A-device or embedded host may repower the VBUS supply at any time (initiate a new session). An OTG B-device may also request that the OTG A-device repower the VBUS supply (initiate a new session). This is accomplished via Session Request Protocol (SRP). Prior to requesting a new session, the B-device must first check that the previous session has definitely ended. To do this, the B-device must check for two conditions: 1. VBUS supply is below the session valid voltage, and 2. Both D+ and D- have been low for at least 2 ms. The B-device will be notified of Condition 1 by the SESENDIF (U1OTGIR<2>) interrupt. Software will have to manually check for Condition 2. Note: When the A-device powers down the VBUS supply, the B-device must disconnect its pull-up resistor from power. If the device is self-powered, it can do this by clearing DPPULUP (U1OTGCON<7>) and DMPULUP (U1OTGCON<6>). The B-device may aid in achieving Condition 1 by discharging the VBUS supply through a resistor. Software may do this by setting VBUSDIS (U1OTGCON<0>). After these initial conditions are met, the B-device may begin requesting the new session. The B-device begins by pulsing the D+ data line. Software should do this by setting DPPULUP (U1OTGCON<7>). The data line should be held high for 5 to 10 ms. The B-device then proceeds by pulsing the VBUS supply. Software should do this by setting PUVBUS (U1CNFG2<4>). When an A-device detects SRP signaling (either via the ATTACHIF (U1IR<6>) interrupt or via the SESVDIF (U1OTGIR<3>) interrupt), the A-device must restore the VBUS supply by either setting VBUSON (U1OTGCON<3>) or by setting the I/O port controlling the external power source. The B-device should not monitor the state of the VBUS supply while performing VBUS supply pulsing. When the B-device does detect that the VBUS supply has been restored (via the SESVDIF (U1OTGIR<3>) interrupt), the B-device must reconnect to the USB link by pulling up D+ or D- (via the DPPULUP or DMPULUP). The A-device must complete the SRP by driving USB Reset signaling. DS39969B-page 252 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.6.2 HOST NEGOTIATION PROTOCOL (HNP) In USB OTG applications, a Dual Role Device (DRD) is a device that is capable of being either a host or a peripheral. Any OTG DRD must support Host Negotiation Protocol (HNP). HNP allows an OTG B-device to temporarily become the USB host. The A-device must first enable the B-device to follow HNP. Refer to the "On-The-Go Supplement to the USB 2.0 Specification" for more information regarding HNP. HNP may only be initiated at full speed. After being enabled for HNP by the A-device, the B-device requests being the host any time that the USB link is in suspend state, by simply indicating a disconnect. This can be done in software by clearing DPPULUP and DMPULUP. When the A-device detects the disconnect condition (via the URSTIF (U1IR<0>) interrupt), the A-device may allow the B-device to take over as host. The A-device does this by signaling connect as a full-speed function. Software may accomplish this by setting DPPULUP. If the A-device responds instead with resume signaling, the A-device remains as host. When the B-device detects the connect condition (via ATTACHIF (U1IR<6>), the B-device becomes host. The B-device drives Reset signaling prior to using the bus. When the B-device has finished in its role as host, it stops all bus activity and turns on its D+ pull-up resistor by setting DPPULUP. When the A-device detects a suspend condition (Idle for 3 ms), the A-device turns off its D+ pull-up. The A-device may also power-down the VBUS supply to end the session. When the A-device detects the connect condition (via ATTACHIF), the A-device resumes host operation and drives Reset signaling. 18.6.3 EXTERNAL VBUS COMPARATORS The external VBUS comparator option is enabled by setting the UVCMPDIS bit (U1CNFG2<1>). This disables the internal VBUS comparators, removing the need to attach VBUS to the microcontroller's VBUS pin. The external comparator interface uses either the VCMPST1 and VCMPST2 pins, or the VBUSVLD, SESSVLD and SESSEND pins, based upon the setting of the UVCMPSEL bit (U1CNFG2<5>). These pins are digital inputs and should be set in the following patterns (see Table 18-3), based on the current level of the VBUS voltage. TABLE 18-3: VCMPST1 0 1 0 1 EXTERNAL VBUS COMPARATOR STATES VCMPST2 0 0 1 1 SESSVLD 0 0 1 1 SESSEND 1 0 0 0 Bus Condition VBUS < VB_SESS_END VB_SESS_END < VBUS < VA_SESS_VLD VA_SESS_VLD < VBUS < VA_VBUS_VLD VBUS > VBUS_VLD Bus Condition VBUS < VB_SESS_END VB_SESS_END < VBUS < VA_SESS_VLD VA_SESS_VLD < VBUS < VA_VBUS_VLD VBUS > VBUS_VLD If UVCMPSEL = 0 If UVCMPSEL = 1 VBUSVLD 0 0 0 1 2010 Microchip Technology Inc. DS39969B-page 253 PIC24FJ256DA210 FAMILY 18.7 USB OTG Module Registers There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: * * * * USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2) With the exception of U1PWMCON and U1PWMRRS, all USB OTG registers are implemented in the Least Significant Byte of the register. Bits in the upper byte are unimplemented and have no function. Note that some registers are instantiated only in Host mode, while other registers have different bit instantiations and functions in Device and Host modes. The registers described in the following sections are those that have bits with specific control and configuration features. The following registers are used for data or address values only: * U1BDTP1: Specifies the 256-word page in data RAM used for the BDT; 8-bit value with bit 0 fixed as `0' for boundary alignment. * U1FRML and U1FRMH: Contains the 11-bit byte counter for the current data frame. * U1PWMRRS: Contains the 8-bit value for PWM duty cycle bits<15:8> and PWM period bits<7:0> for the VBUS boost assist PWM module. This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 18-1 and Register 18-2, are shown separately in Section 18.2 "USB Buffer Descriptors and the BDT". DS39969B-page 254 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.7.1 USB OTG MODULE CONTROL REGISTERS U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- R-0, HSC LSTATE U-0 -- R-0, HSC SESVD R-0, HSC SESEND U-0 -- R-0, HSC VBUSVD bit 0 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit `0' = Bit is cleared x = Bit is unknown REGISTER 18-3: U-0 -- bit 15 R-0, HSC ID bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 Unimplemented: Read as `0' ID: ID Pin State Indicator bit 1 = No plug is attached, or a type B cable has been plugged into the USB receptacle 0 = A type A plug has been plugged into the USB receptacle Unimplemented: Read as `0' LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms 0 = The USB line state has not been stable for the previous 1 ms Unimplemented: Read as `0' SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device SESEND: B Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the B-device 0 = The VBUS voltage is above VB_SESS_END on the B-device Unimplemented: Read as `0' VBUSVD: A VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2010 Microchip Technology Inc. DS39969B-page 255 PIC24FJ256DA210 FAMILY REGISTER 18-4: U-0 -- bit 15 R/W-0 DPPULUP bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DMPULUP R/W-0 R/W-0 R/W-0 VBUSON(1) R/W-0 OTGEN(1) R/W-0 U-0 -- U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 bit 0 DPPULDWN(1) DMPULDWN(1) VBUSCHG(1) VBUSDIS(1) Unimplemented: Read as `0' DPPULUP: D+ Pull-up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled DMPULUP: D- Pull-up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled VBUSON: VBUS Power-on bit(1) 1 = VBUS line is powered 0 = VBUS line is not powered OTGEN: OTG Features Enable bit(1) 1 = USB OTG is enabled; all D+/D- pull-up and pull-down bits are enabled 0 = USB OTG is disabled; D+/D- pull-up and pull-down bits are controlled in hardware by the settings of the HOSTEN and USBEN (U1CON<3,0>) bits VBUSCHG: VBUS Charge Select bit(1) 1 = VBUS line is set to charge to 3.3V 0 = VBUS line is set to charge to 5V VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line is discharged through a resistor 0 = VBUS line is not discharged These bits are only used in Host mode; do not use in Device mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39969B-page 256 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-5: U-0 -- bit 15 R/W-0, HS UACTPND bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 HS = Hardware Settable bit W = Writable bit `1' = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 USLPGRD U-0 -- U-0 -- R/W-0, HC USUSPND U1PWRC: USB POWER CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 USBPWR bit 0 Unimplemented: Read as `0' UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires the USLPGRD bit to be set) 0 = Module may be suspended or powered down Unimplemented: Read as `0' USLPGRD: Sleep/Suspend Guard bit 1 = Indicate to the USB module that it is about to be suspended or powered down 0 = No suspend Unimplemented: Read as `0' USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a low-power state 0 = Normal USB OTG operation USBPWR: USB Operation Enable bit 1 = USB OTG module is enabled 0 = USB OTG module is disabled(1) Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON<3,0> and U1OTGCON<2>) are all cleared. bit 6-5 bit 4 bit 3-2 bit 1 bit 0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 257 PIC24FJ256DA210 FAMILY REGISTER 18-6: U-0 -- bit 15 R-0, HSC ENDPT3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit `0' = Bit is cleared x = Bit is unknown R-0, HSC ENDPT2 R-0, HSC ENDPT1 R-0, HSC ENDPT0 R-0, HSC DIR R-0, HSC PPBI(1) U-0 -- U-0 -- bit 0 U1STAT: USB STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 Unimplemented: Read as `0' ENDPT<3:0>: Number of the Last Endpoint Activity bits (Represents the number of the BDT updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 . . . 0001 = Endpoint 1 0000 = Endpoint 0 DIR: Last BD Direction Indicator bit 1 = The last transaction was a transmit transfer (TX) 0 = The last transaction was a receive transfer (RX) PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the odd BD bank 0 = The last transaction was to the even BD bank Unimplemented: Read as `0' This bit is only valid for endpoints with available even and odd BD registers. bit 3 bit 2 bit 1-0 Note 1: DS39969B-page 258 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-7: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit `0' = Bit is cleared x = Bit is unknown R-x, HSC SE0 R/W-0 PKTDIS U-0 -- R/W-0 HOSTEN R/W-0 RESUME R/W-0 PPBRST U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 USBEN bit 0 Unimplemented: Read as `0' SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing are disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing are enabled Unimplemented: Read as `0' HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated 0 = Resume signaling is disabled PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the even BD banks 0 = Ping-Pong Buffer Pointers are not reset USBEN: USB Module Enable bit 1 = USB module and supporting circuitry are enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry are disabled (device detached) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2010 Microchip Technology Inc. DS39969B-page 259 PIC24FJ256DA210 FAMILY REGISTER 18-8: U-0 -- bit 15 R-x, HSC JSTATE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit `0' = Bit is cleared x = Bit is unknown R-x, HSC SE0 R/W-0 TOKBUSY R/W-0 USBRST R/W-0 HOSTEN R/W-0 RESUME R/W-0 PPBRST U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 SOFEN bit 0 Unimplemented: Read as `0' JSTATE: Live Differential Receiver J State Flag bit 1 = J state (differential `0' in low speed, differential `1' in full speed) is detected on the USB 0 = No J state is detected SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected TOKBUSY: Token Busy Status bit 1 = Token is being executed by the USB module in On-The-Go state 0 = No token is being executed USBRST: Module Reset bit 1 = USB Reset has been generated; for software Reset, application must set this bit for 50 ms, then clear it 0 = USB Reset is terminated HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated; software must set bit for 10 ms and then clear to enable remote wake-up 0 = Resume signaling is disabled PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the even BD banks 0 = Ping-Pong Buffer Pointers are not reset SOFEN: Start-Of-Frame Enable bit 1 = Start-Of-Frame token is sent every one 1 ms 0 = Start-Of-Frame token is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39969B-page 260 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-9: U-0 -- bit 15 R/W-0 LSPDEN(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ADDR6 R/W-0 ADDR5 R/W-0 ADDR4 R/W-0 ADDR3 R/W-0 ADDR2 R/W-0 ADDR1 U1ADDR: USB ADDRESS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 ADDR0 bit 0 Unimplemented: Read as `0' LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB module operates at low speed 0 = USB module operates at full speed ADDR<6:0>: USB Device Address bits Host mode only. In Device mode, this bit is unimplemented and read as `0'. bit 6-0 Note 1: REGISTER 18-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY) U-0 -- bit 15 R/W-0 PID3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PID2 R/W-0 PID1 R/W-0 PID0 R/W-0 EP3 R/W-0 EP2 R/W-0 EP1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 EP0 bit 0 Unimplemented: Read as `0' PID<3:0>: Token Type Identifier bits 1101 = SETUP (TX) token type transaction(1) 1001 = IN (RX) token type transaction(1) 0001 = OUT (TX) token type transaction(1) EP<3:0>: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. All other combinations are reserved and are not to be used. bit 3-0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 261 PIC24FJ256DA210 FAMILY REGISTER 18-11: U-0 -- bit 15 R/W-0 CNT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 R/W-0 CNT6 R/W-0 CNT5 R/W-0 CNT4 R/W-0 CNT3 R/W-0 CNT2 R/W-0 CNT1 U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 CNT0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' CNT<7:0>: Start-Of-Frame Size bits Value represents 10 + (packet size of n bytes). For example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet REGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1 U-0 -- bit 15 R/W-0 UTEYE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 UOEMON(1) U-0 -- R/W-0 USBSIDL U-0 -- U-0 -- R/W-0 PPB1 R/W-0 PPB0 bit 0 Unimplemented: Read as `0' UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive Unimplemented: Read as `0' USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' PPB<1:0>: Ping-Pong Buffers Configuration bits 11 = Even/Odd ping-pong buffers are enabled for Endpoints 1 to 15 10 = Even/Odd ping-pong buffers are enabled for all endpoints 01 = Even/Odd ping-pong buffers are enabled for OUT Endpoint 0 00 = Even/Odd ping-pong buffers are disabled This bit is only active when the UTRDIS bit (U1CNFG2<0>) is set. bit 6 bit 5 bit 4 bit 3-2 bit 1-0 Note 1: DS39969B-page 262 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 UVCMPSEL R/W-0 PUVBUS R/W-0 EXTI2CEN R/W-0 UVBUSDIS(1) R/W-0 UVCMPDIS(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 UTRDIS(1) bit 0 Unimplemented: Read as `0' UVCMPSEL: VBUS Comparator External Interface Selection bit 1 = Use VBUSVLD, SESSVLD and SESSEND as comparator interface pins 0 = Use VCMPST1 and VCMPST2 as comparator interface pins PUVBUS: VBUS Pull-Up Enable bit 1 = Pull-up on VBUS pin is enabled 0 = Pull-up on VBUS pin is disabled EXTI2CEN: I2CTM Interface For External Module Control Enable bit 1 = External module(s) is controlled via the I2CTM interface 0 = External module(s) controlled via the dedicated pins UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder is disabled; digital output control interface is enabled 0 = On-chip boost regulator builder is active UVCMPDIS: On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator is disabled; digital input status interface is enabled 0 = On-chip charge VBUS comparator is active UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver is disabled; digital transceiver interface is enabled 0 = On-chip transceiver is active Never change these bits while the USBPWR bit is set (U1PWRC<0> = 1). bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 263 PIC24FJ256DA210 FAMILY 18.7.2 USB INTERRUPT REGISTERS REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 -- bit 15 R/K-0, HS IDIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as `0' K = Write `1' to clear bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared x = Bit is unknown R/K-0, HS T1MSECIF R/K-0, HS LSTATEIF R/K-0, HS ACTVIF R/K-0, HS SESVDIF R/K-0, HS SESENDIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/K-0, HS VBUSVDIF bit 0 Unimplemented: Read as `0' IDIF: ID State Change Indicator bit 1 = Change in ID state is detected 0 = No ID state change is detected T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from the last time 0 = USB line state has not been stable for 1 ms ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS is detected 0 = No activity on the D+/D- lines or VBUS is detected SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device detected; VBUS has crossed VB_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END Unimplemented: Read as `0' VBUSVDIF: A-Device VBUS Change Indicator bit 1 = VBUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB OTG Specification)(1) 0 = No VBUS change on A-device is detected VBUS threshold crossings may be either rising or falling. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Note: Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39969B-page 264 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 -- bit 15 R/W-0 IDIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 T1MSECIE R/W-0 LSTATEIE R/W-0 ACTVIE R/W-0 SESVDIE R/W-0 SESENDIE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 VBUSVDIE bit 0 Unimplemented: Read as `0' IDIE: ID Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as `0' VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2010 Microchip Technology Inc. DS39969B-page 265 PIC24FJ256DA210 FAMILY REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 -- bit 15 R/K-0, HS STALLIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as `0' K = Write `1' to clear bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared x = Bit is unknown U-0 -- R/K-0, HS RESUMEIF R/K-0, HS IDLEIF R/K-0, HS TRNIF R/K-0, HS SOFIF R-0 UERRIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/K-0, HS URSTIF bit 0 Unimplemented: Read as `0' STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent Unimplemented: Read as `0' RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential `1' for low speed, differential `0' for full speed) 0 = No K-state is observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3 ms or more) 0 = No Idle condition is detected TRNIF: Token Processing Complete Interrupt bit 1 = Processing of the current token is complete; read the U1STAT register for endpoint information 0 = Processing of the current token is not complete; clear the U1STAT register or load the next token from STAT (clearing this bit causes the STAT FIFO to advance) SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token is received by the peripheral or the Start-Of-Frame threshold is reached by the host 0 = No Start-Of-Frame token is received or threshold reached UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: DS39969B-page 266 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 -- bit 15 R/K-0, HS STALLIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as `0' K = Write `1' to clear bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared x = Bit is unknown R/K-0, HS ATTACHIF R/K-0, HS RESUMEIF R/K-0, HS IDLEIF R/K-0, HS TRNIF R/K-0, HS SOFIF R-0 UERRIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/K-0, HS DETACHIF bit 0 Unimplemented: Read as `0' STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; it is set if the bus state is not SE0 and there has been no bus activity for 2.5 s 0 = No peripheral attacement has been detected RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential `1' for low speed, differential `0' for full speed) 0 = No K-state is observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3 ms or more) 0 = No Idle condition is detected TRNIF: Token Processing Complete Interrupt bit 1 = Processing of the current token is complete; read the U1STAT register for endpoint information 0 = Processing of the current token not complete; clear the U1STAT register or load the next token from U1STAT SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module; Reset state must be cleared before this bit can be reasserted 0 = No peripheral detachment is detected. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: 2010 Microchip Technology Inc. DS39969B-page 267 PIC24FJ256DA210 FAMILY REGISTER 18-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 -- bit 15 R/W-0 STALLIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ATTACHIE (1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 RESUMEIE R/W-0 IDLEIE R/W-0 TRNIE R/W-0 SOFIE R/W-0 UERRIE R/W-0 URSTIE DETACHIE bit 0 Unimplemented: Read as `0' STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)(1) 1 = Interrupt is enabled 0 = Interrupt is disabled RESUMEIE: Resume Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled IDLEIE: Idle Detect Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled SOFIE: Start-Of-Frame Token Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled UERRIE: USB Error Condition Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented in Device mode, read as `0'. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39969B-page 268 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 -- bit 15 R/K-0, HS BTSEF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as `0' K = Write `1' to clear bit `1' = Bit is set HS = Hardware Settable bit `0' = Bit is cleared x = Bit is unknown U-0 -- R/K-0, HS DMAEF R/K-0, HS BTOEF R/K-0, HS DFN8EF R/K-0, HS CRC16EF R/K-0, HS CRC5EF EOFEF bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/K-0, HS PIDEF Unimplemented: Read as `0' BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error has been detected Unimplemented: Read as `0' DMAEF: DMA Error Flag bit 1 = A USB DMA error condition is detected; the data size indicated by the BD byte count field is less than the number of received bytes, the received data is truncated 0 = No DMA error BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed For Device mode: CRC5EF: CRC5 Host Error Flag bit 1 = Token packet is rejected due to CRC5 error 0 = Token packet is accepted (no CRC5 error) For Host mode: EOFEF: End-Of-Frame Error Flag bit 1 = End-Of-Frame error has occurred 0 = End-Of-Frame interrupt is disabled PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. 2010 Microchip Technology Inc. DS39969B-page 269 PIC24FJ256DA210 FAMILY REGISTER 18-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 -- bit 15 R/W-0 BTSEE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 DMAEE R/W-0 BTOEE R/W-0 DFN8EE R/W-0 CRC16EE R/W-0 CRC5EE EOFEE bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PIDEE Unimplemented: Read as `0' BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as `0' DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled For Device mode: CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled For Host mode: EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39969B-page 270 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.7.3 U-0 -- bit 15 R/W-0 LSPD(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 RETRYDIS(1) U-0 -- R/W-0 EPCONDIS R/W-0 EPRXEN R/W-0 EPTXEN R/W-0 EPSTALL USB ENDPOINT MANAGEMENT REGISTERS U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 EPHSHK bit 0 REGISTER 18-21: U1EPn: USB ENDPOINT n CONTROL REGISTERS (n = 0 TO 15) Unimplemented: Read as `0' LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)(1) 1 = Direct connection to a low-speed device is enabled 0 = Direct connection to a low-speed device is disabled RETRYDIS: Retry Disable bit (U1EP0 only)(1) 1 = Retry NAK transactions is disabled 0 = Retry NAK transactions is enabled; retry is done in hardware Unimplemented: Read as `0' EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN and EPRXEN = 1: 1 = Disable Endpoint n from control transfers; only TX and RX transfers are allowed 0 = Enable Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed For all other combinations of EPTXEN and EPRXEN: This bit is ignored. EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake is enabled 0 = Endpoint handshake is disabled (typically used for isochronous endpoints) These bits are available only for U1EP0 and only in Host mode. For all other U1EPn registers, these bits are always unimplemented and read as `0'. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 271 PIC24FJ256DA210 FAMILY 18.7.4 USB VBUS POWER CONTROL REGISTER REGISTER 18-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER R/W-0 PWMEN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PWMPOL R/W-0 CNTEN bit 8 PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in the Reset state specified by PWMPOL Unimplemented: Read as `0' PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled Unimplemented: Read as `0' bit 14-10 bit 9 bit 8 bit 7-0 DS39969B-page 272 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 19.0 Note: ENHANCED PARALLEL MASTER PORT (EPMP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 42. "Enhanced Parallel Master Port (EPMP)" (DS39730). The information in this data sheet supersedes the information in the FRM. Key features of the EPMP module are: * Extended Data Space (EDS) interface allows Direct Access from the CPU * Up to 23 Programmable Address Lines * Up to 2 Chip Select Lines * Up to 2 Acknowledgement Lines (one per chip select) * 4-bit, 8-bit or 16-bit wide Data Bus * Programmable Strobe Options (per chip select) - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe * Programmable Address/Data Multiplexing * Programmable Address Wait States * Programmable Data Wait States (per chip select) * Programmable Polarity on Control Signals (per chip select) * Legacy Parallel Slave Port Support * Enhanced Parallel Slave Support - Address Support - 4-Byte Deep Auto-Incrementing Buffer * Alternate Master feature The Enhanced Parallel Master Port (EPMP) module is present in PIC24FJXXXDAX10 devices and not in PIC24FJXXXDAX06 devices. The EPMP provides a parallel 4-bit (Master mode only), 8-bit (Master and Slave modes) or 16-bit (Master mode only) data bus interface to communicate with off-chip modules, such as memories, FIFOs, LCD controllers and other microcontrollers. This module can serve as either the master or the slave on the communication bus. For EPMP Master modes, all external addresses are mapped into the internal Extended Data Space (EDS). This is done by allocating a region of the EDS for each chip select, and then assigning each chip select to a particular external resource, such as a memory or external controller. This region should not be assigned to another device resource, such as RAM or SFRs. To perform a write or read on an external resource, the CPU should simply perform a write or read within the address range assigned for EPMP. Note: The EPMP module is not present in 64-pin devices (PIC24FJXXXDAX06). 19.1 ALTPMP Setting Many of the lower order EPMP address pins are shared with ADC inputs. This is an untenable situation for users that need both the ADC channels and the EPMP bus. If the user does not need to use all the address bits, then by clearing the ALTPMP (CW3<12>) Configuration bit, the lower order address bits can be mapped to higher address pins, which frees the ADC channels. The EPMP has an alternative master feature. The graphics controller module can control the EPMP directly in Alternate Master mode to access an external graphics buffer. TABLE 19-1: Pin RA14 RC4 RF12 RG6 RG7 RA3 RG8 RA4 ALTERNATE EPMP PINS ALTPMP = 0 PMCS2 PMA22 PMA5 PMA18 PMA20 PMA4 PMA21 PMA3 ALTPMP = 1 PMA22 PMCS2 PMA18 PMA5 PMA4 PMA20 PMA3 PMA21 2010 Microchip Technology Inc. DS39969B-page 273 PIC24FJ256DA210 FAMILY TABLE 19-2: PARALLEL MASTER PORT PIN DESCRIPTION Type O O PMA<15>, PMCS2 O I/O O PMA<14>, PMCS1 O I/O O PMA<13:8> PMA<7:3> PMA<2>, PMALU I/O O O O PMA<1>, PMALH PMA<0>, PMALL PMD<15:8> PMD<7:4> PMD<3:0> PMCS1 PMCS2 PMWR, PMENB PMRD, PMRD/PMWR PMBE1 PMBE0 PMACK1 PMACK2 I/O O I/O O I/O I/O O I/O I/O O I/O I/O O O I I Address bus bit<15> Chip Select 2 (alternate location) Data bus bit<15> when port size is 16 bits and address is multiplexed Address bus bit<14> Chip Select 1 (alternate location) Data bus bit 14 when port size is 16-bit and address is multiplexed Address bus bit< 13-8> Data bus bits<13-8> when port size is 16 bits and address is multiplexed Address bus bit< 7-3> Address bus bit<2> Address latch upper strobe for multiplexed address Address bus bit<1> Address latch high strobe for multiplexed address Address bus bit<0> Address latch low strobe for multiplexed address Data bus bits<15-8> when address is not multiplexed Data bus bits<7-4> Address bus bits<7-4> when port size is 4 bits and address is multiplexed with 1 address phase Data bus bits<3-0> Chip Select 1 Chip Select 2 Write strobe or Enable signal depending on Strobe mode Read strobe or Read/Write signal depending on Strobe mode Byte indicator Nibble or byte indicator Acknowledgment 1 Acknowledgment 2 Description Address bus bits<22-16> Pin Name PMA<22:16> DS39969B-page 274 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-1: R/W-0 PMPEN bit 15 R/W-0 CSF1 bit 7 PMCON1: EPMP CONTROL REGISTER 1 U-0 -- R/W-0 PSIDL R/W-0 ADRMUX1 R/W-0 ADRMUX0 U-0 -- R/W-0 MODE1 R/W-0 MODE0 bit 8 R/W-0 IRQM0 bit 0 R/W-0 CSF0 R/W-0 ALP R/W-0 ALMODE U-0 -- R/W-0 BUSKEEP R/W-0 IRQM1 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12-11 bit 10 bit 9-8 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1-0 PMPEN: Parallel Master Port Enable bit 1 = EPMP is enabled 0 = EPMP is disabled Unimplemented: Read as `0' PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower address bits are multiplexed with data bits using 3 address phases 10 = Lower address bits are multiplexed with data bits using 2 address phases 01 = Lower address bits are multiplexed with data bits using 1 address phase 00 = Address and data appear on separate pins Unimplemented: Read as `0' MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 10 = Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0> 01 = Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD<7:0> 00 = Legacy Parallel Slave Port; PMRD, PMWR, PMCS and PMD<7:0> pins are used CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = PMA<15> used for Chip Select 2, PMA<14> used for Chip Select 1 01 = PMA<15> used for Chip Select 2, PMCS1 used for Chip Select 1 00 = PMCS2 used for Chip Select 2, PMCS1 used for Chip Select 1 ALP: Address Latch Polarity bit 1 = Active-high (PMALL, PMALH and PMALU) 0 = Active-low (PMALL, PMALH and PMALU) ALMODE: Address Latch Strobe Mode bit 1 = Enable "smart" address strobes (each address phase is only present if the current access would cause a different address in the latch than the previous address) 0 = Disable "smart" address strobes Unimplemented: Read as `0' BUSKEEP: Bus Keeper bit 1 = Data bus keeps its last value when not actively being driven 0 = Data bus is in high-impedance state when not actively being driven IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt generated at the end of a read/write cycle 00 = No interrupt is generated 2010 Microchip Technology Inc. DS39969B-page 275 PIC24FJ256DA210 FAMILY REGISTER 19-2: R-0, HSC BUSY bit 15 R/W-0 RADDR23 bit 7 R/W-0 RADDR22 R/W-0 RADDR21 R/W-0 RADDR20 R/W-0 RADDR19 R/W-0 RADDR18 R/W-0 RADDR17 U-0 -- PMCON2: EPMP CONTROL REGISTER 2 R/C-0, HS ERROR R/C-0, HS TIMEOUT R-0, HSC AMREQ R-1, HSC CURMST R/W-0 MSTSEL1 R/W-0 MSTSEL0 bit 8 R/W-0 RADDR16 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' C = Clearable bit `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7-0 Note 1: BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy Unimplemented: Read as `0' ERROR: Error bit 1 = Transaction error (illegal transaction was requested) 0 = Transaction completed successfully TIMEOUT: Time-Out bit 1 = Transaction timed out 0 = Transaction completed successfully AMREQ: Alternate Master Request bit 1 = The Alternate Master is requesting use of EPMP 0 = The Alternate Master is not requesting use of EPMP CURMST: Current Master bit 1 = EPMP access is granted to CPU 0 = EPMP access is granted to alternate master MSTSEL<1:0>: Parallel Port Master Select bits 11 = Alternate master I/Os direct access (EPMP Bypass mode) 10 = Reserved 01 = Alternate master 00 = CPU RADDR<23:16>: Parallel Master Port Reserved Address Space bits(1) If RADDR<23:16> = 00000000, then the last EDS address for Chip Select 2 will be 0xFFFFFF. DS39969B-page 276 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-3: R/W-0 PTWREN bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 PMCON3: EPMP CONTROL REGISTER 3 R/W-0 PTBE1EN R/W-0 PTBE0EN U-0 -- R/W-0 AWAITM1 R/W-0 AWAITM0 R/W-0 AWAITE bit 8 R/W-0 PTEN16 bit 0 R/W-0 PTRDEN R/W-0 PTEN22 R/W-0 PTEN21 R/W-0 PTEN20 R/W-0 PTEN19 R/W-0 PTEN18 R/W-0 PTEN17 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12 bit 11 bit 10-9 bit bit 8 bit 7 bit 6-0 PTWREN: Write/Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled PTBE1EN: High Nibble/Byte Enable Port Enable bit 1 = PMBE1 port is enabled 0 = PMBE1 port is disabled PTBE0EN: Low Nibble/Byte Enable Port Enable bit 1 = PMBE0 port is enabled 0 = PMBE0 port is disabled Unimplemented: Read as `0' AWAITM<1:0>: Address Latch Strobe Wait States bits 11 = Wait of 31/2 TCY 10 = Wait of 21/2 TCY 01 = Wait of 11/2 TCY 00 = Wait of 1/2 TCY AWAITE: Address Hold After Address Latch Strobe Wait States bits 1 = Wait of 11/4 TCY 0 = Wait of 1/4 TCY Unimplemented: Read as `0' PTEN<22:16>: EPMP Address Port Enable bits 1 = PMA<22:16> function as EPMP address lines 0 = PMA<22:16> function as port I/Os 2010 Microchip Technology Inc. DS39969B-page 277 PIC24FJ256DA210 FAMILY REGISTER 19-4: R/W-0 PTEN15 bit 15 R/W-0 PTEN7 bit 7 PMCON4: EPMP CONTROL REGISTER 4 R/W-0 PTEN13 R/W-0 PTEN12 R/W-0 PTEN11 R/W-0 PTEN10 R/W-0 PTEN9 R/W-0 PTEN8 bit 8 R/W-0 PTEN0 bit 0 R/W-0 PTEN14 R/W-0 PTEN6 R/W-0 PTEN5 R/W-0 PTEN4 R/W-0 PTEN3 R/W-0 PTEN2 R/W-0 PTEN1 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13-3 bit 2-0 PTEN15: PMA15 Port Enable bit 1 = PMA15 functions as either Address Line 15 or Chip Select 2 0 = PMA15 functions as port I/O PTEN14: PMA14 Port Enable bit 1 = PMA14 functions as either Address Line 14 or Chip Select 1 0 = PMA14 functions as port I/O PTEN<13:3>: EPMP Address Port Enable bits 1 = PMA<13:3> function as EPMP address lines 0 = PMA<13:3> function as port I/Os PTEN<2:0>: PMALU/PMALH/PMALL Strobe Enable bits 1 = PMA<2:0> function as either address lines or address latch strobes 0 = PMA<2:0> function as port I/Os DS39969B-page 278 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-5: R/W-0 CSDIS bit 15 R/W-0 ACKP bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PTSZ1 R/W-0 PTSZ0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER R/W-0 CSPTEN R/W-0 BEP U-0 -- R/W-0 WRSP R/W-0 RDSP R/W-0 SM bit 8 CSP R/W-0 CSDIS: Chip Select x Disable bit 1 = Disable the Chip Select x functionality 0 = Enable the Chip Select x functionality CSP: Chip Select x Polarity bit 1 = Active-high (PMCSx) 0 = Active-low (PMCSx) CSPTEN: PMCSx Port Enable bit 1 = PMCSx port is enabled 0 = PMCSx port is disabled BEP: Chip Select x Nibble/Byte Enable Polarity bit 1 = Nibble/Byte enable active-high (PMBE0, PMBE1) 0 = Nibble/Byte enable active-low (PMBE0, PMBE1) Unimplemented: Read as `0' WRSP: Chip Select x Write Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode when SM = 1: 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Chip Select x Read Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode when SM = 1: 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/Write strobe active-low (PMRD/PMWR) SM: Chip Select x Strobe Mode bit 1 = Read/Write and enable strobes (PMRD/PMWR and PMENB) 0 = Read and write strobes (PMRD and PMWR) ACKP: Chip Select x Acknowledge Polarity bit 1 = ACK active-high (PMACK1) 0 = ACK active-low (PMACK1) PTSZ<1:0>: Chip Select x Port Size bits 11 = Reserved 10 = 16-bit port size (PMD<15:0>) 01 = 4-bit port size (PMD<3:0>) 00 = 8-bit port size (PMD<7:0>) Unimplemented: Read as `0' bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-5 bit 4-0 2010 Microchip Technology Inc. DS39969B-page 279 PIC24FJ256DA210 FAMILY REGISTER 19-6: R/W(1) BASE23 bit 15 R/W(1) BASE15 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 bit 3 bit 2-0 Note 1: 2: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W(1) BASE11 U-0 -- U-0 -- U-0 -- bit 0 PMCSxBS: CHIP SELECT x BASE ADDRESS REGISTER R/W(1) BASE21 R/W(1) BASE20 R/W(1) BASE19 R/W(1) BASE18 R/W(1) BASE17 R/W(1) BASE16 bit 8 R/W(1) BASE22 BASE<23:15>: Chip Select x Base Address bits(2) Unimplemented: Read as `0' BASE<11>: Chip Select x Base Address bits(2) Unimplemented: Read as `0' Value at POR is 0x0200 for PMCS1BS and 0x0600 for PMCS2BS. If the whole PMCS2BS register is written together as 0x0000, then the last EDS address for the Chip Select 1 will be 0xFFFFFF. In this case, the Chip Select 2 should not be used. PMCS1BS has no such feature. DS39969B-page 280 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-7: R/W-0 ACKM1 bit 15 R/W-0 DWAITB1 bit 7 PMCSxMD: CHIP SELECT x MODE REGISTER R/W-0 AMWAIT2 R/W-0 AMWAIT1 R/W-0 AMWAIT0 U-0 -- U-0 -- U-0 -- bit 8 R/W-0 ACKM0 R/W-0 DWAITB0 R/W-0 DWAITM3 R/W-0 DWAITM2 R/W-0 DWAITM1 R/W-0 DWAITM0 R/W-0 DWAITE1 R/W-0 DWAITE0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 13-11 ACKM<1:0>: Chip Select x Acknowledge Mode bits 11 = Reserved 10 = PMACKx is used to determine when a read/write operation is complete 01 = PMACKx is used to determine when a read/write operation is complete with time-out If DWAITM<3:0> = 0000, the maximum time-out is 255 TCY, else it is DWAITM<3:0> cycles. 00 = PMACKx is not used AMWAIT<2:0>: Chip Select x Alternate Master Wait States bits 111 = Wait of 10 alternate master cycles ... bit 10-8 bit 7-6 bit 5-2 001 = Wait of 4 alternate master cycles 000 = Wait of 3 alternate master cycles Unimplemented: Read as `0' DWAITB<1:0>: Chip Select x Data Setup Before Read/Write Strobe Wait States bits 11 = Wait of 31/4 TCY 10 = Wait of 21/4 TCY 01 = Wait of 11/4 TCY 00 = Wait of 1/4 TCY DWAITM<3:0>: Chip Select x Data Read/Write Strobe Wait States bits For Write operations: 1111 = Wait of 151/2 TCY ... 0001 = Wait of 11/2 TCY 0000 = Wait of 1/2 TCY For Read operations: 1111 = Wait of 153/4 TCY ... bit 1-0 0001 = Wait of 13/4 TCY 0000 = Wait of 3/4 TCY DWAITE<1:0>: Chip Select x Data Hold After Read/Write Strobe Wait States bits For Write operations: 11 = Wait of 31/4 TCY 10 = Wait of 21/4 TCY 01 = Wait of 11/4 TCY 00 = Wait of 1/4 TCY For Read operations: 11 = Wait of 3 TCY 10 = Wait of 2 TCY 01 = Wait of 1 TCY 00 = Wait of 0 TCY 2010 Microchip Technology Inc. DS39969B-page 281 PIC24FJ256DA210 FAMILY REGISTER 19-8: R-0, HSC IBF bit 15 R-1, HSC OBE bit 7 PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY) U-0 -- U-0 -- R-0, HSC IB3F R-0, HSC IB2F R-0, HSC IB1F R-0, HSC IB0F bit 8 R-1, HSC OB0E bit 0 R/W-0 HS IBOV R/W-0 HS OBUF U-0 -- U-0 -- R-1, HSC OB3E R-1, HSC OB2E R-1, HSC OB1E Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14 bit 13-12 bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as `0' IBxF: Input Buffer x Status Full bit(1) 1 = Input buffer contains unread data (reading buffer will clear this bit) 0 = Input buffer does not contain unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as `0' OBxE: Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains untransmitted data Even though an individual bit represents the byte in the buffer, the bits corresponding to the Word (byte 0 and 1, or byte 2 and 3) gets cleared even on byte reading. Note 1: DS39969B-page 282 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-9: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 RTSECSEL(1) PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 PMPTTL(2) bit 0 Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: EPMP Module TTL Input Buffer Select bit(2) 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit must also be set. Unimplemented in 64-pin devices (PIC24FJXXXDAX06); maintain as `0'. bit 0 Note 1: 2: 2010 Microchip Technology Inc. DS39969B-page 283 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 284 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 20.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 29. "Real-Time Clock and Calendar (RTCC)" (DS39696). The information in this data sheet supersedes the information in the FRM. The Real-Time Clock and Calendar (RTCC) provides a function that can be calibrated. Key features of the RTCC module are: * Operates in Sleep mode * Provides hours, minutes and seconds using 24-hour format * Visibility of half of one second period * Provides calendar - weekday, date, month and year * Alarm configurable for half a second, one second,10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year * Alarm repeat with decrementing counter * Alarm with indefinite repeat chime * Year, 2000 to 2099, leap year correction * BCD format for smaller software overhead * Optimized for long-term battery operation * User calibration of the 32.768 kHz clock crystal/32K INTRC frequency with periodic auto-adjust - Calibration to within 2.64 seconds error per month - Calibrates up to 260 ppm of crystal error FIGURE 20-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain RCFGCAL RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL ALCFGRPT YEAR MTHDY WKDYHR MINSEC ALMTHDY Compare Registers with Masks Repeat Counter ALRMVAL ALWDHR ALMINSEC 32.768 kHz Input from SOSC Comparator RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE 2010 Microchip Technology Inc. DS39969B-page 285 PIC24FJ256DA210 FAMILY 20.1 RTCC Module Registers TABLE 20-2: ALRMPTR <1:0> 00 01 10 11 The RTCC module registers are organized into three categories: * RTCC Control Registers * RTCC Value Registers * Alarm Value Registers ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMWD ALRMMNTH -- ALRMSEC ALRMHR ALRMDAY -- 20.1.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through the corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 20-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR<1:0> bits, decrement by one until they reach `00'. Once they reach `00', the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes, they will decrement the ALRMPTR<1:0> value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR<1:0> being decremented. Note: This only applies to read operations and not write operations. 20.1.2 WRITE LOCK TABLE 20-1: RTCPTR <1:0> 00 01 10 11 RTCVAL REGISTER MAPPING RTCC Value Register Window RTCVAL<15:8> MINUTES WEEKDAY MONTH -- RTCVAL<7:0> SECONDS HOURS DAY YEAR The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>) to select the desired Alarm register pair (see Table 20-2). By writing the ALRMVALH byte, the Alarm Pointer value bits, ALRMPTR<1:0>, decrement by one until they reach `00'. Once they reach `00', the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. In order to perform a write to any of the RTCC Timer registers, the RTCWREN (RCFGCAL<13>) bit must be set (refer to Example 20-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL<13>) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the unlock sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 20-1. For applications written in C, the unlock sequence should be implemented using in-line assembly. EXAMPLE 20-1: asm asm asm asm asm asm SETTING THE RTCWREN BIT volatile("disi #5"); volatile("mov #0x55, w7"); volatile("mov w7, _NVMKEY"); volatile("mov #0xAA, w8"); volatile("mov w8, _NVMKEY"); volatile("bset _RCFGCAL, #13"); //set the RTCWREN bit DS39969B-page 286 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 20.1.3 RTCC CONTROL REGISTERS RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) U-0 -- R/W-0 RTCWREN R-0, HSC RTCSYNC R-0, HSC HALFSEC (3) REGISTER 20-1: R/W-0 RTCEN(2) bit 15 R/W-0 CAL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 RTCOE R/W-0, HSC RTCPTR1 R/W-0, HSC RTCPTR0 bit 8 R/W-0 CAL6 R/W-0 CAL5 R/W-0 CAL4 R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as `0' RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches `00'. RTCVAL<15:8>: 11 = Reserved 10 = MONTH 01 = WEEKDAY 00 = MINUTES RTCVAL<7:0>: 11 = YEAR 10 = DAY 01 = HOURS 00 = SECONDS The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 Note 1: 2: 3: 2010 Microchip Technology Inc. DS39969B-page 287 PIC24FJ256DA210 FAMILY REGISTER 20-1: bit 7-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment . . . 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute Note 1: 2: 3: The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register. REGISTER 20-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 RTSECSEL(1) R/W-0 PMPTTL bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: EPMP Module TTL Input Buffer Select bit 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit must also be set. bit 0 Note 1: DS39969B-page 288 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 20-3: R/W-0 ALRMEN bit 15 R/W-0, HSC ARPT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HSC ARPT6 R/W-0, HSC ARPT5 R/W-0, HSC ARPT4 R/W-0, HSC ARPT3 R/W-0, HSC ARPT2 R/W-0, HSC ARPT1 ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0, HSC ALRMPTR1 R/W-0, HSC ALRMPTR0 bit 8 R/W-0, HSC ARPT0 bit 0 R/W-0 CHIME ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and CHIME = 0) 0 = Alarm is disabled CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h AMASK<3:0>: Alarm Mask Configuration bits 11xx = Reserved - do not use 101x = Reserved - do not use 1001 = Once a year (except when configured for February 29th, once every 4 years) 1000 = Once a month 0111 = Once a week 0110 = Once a day 0101 = Every hour 0100 = Every 10 minutes 0011 = Every minute 0010 = Every 10 seconds 0001 = Every second 0000 = Every half second ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches `00'. ALRMVAL<15:8>: 11 = Unimplemented 10 = ALRMMNTH 01 = ALRMWD 00 = ALRMMIN ALRMVAL<7:0>: 11 = Unimplemented 10 = ALRMDAY 01 = ALRMHR 00 = ALRMSEC ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. bit 14 bit 13-10 bit 9-8 bit 7-0 2010 Microchip Technology Inc. DS39969B-page 289 PIC24FJ256DA210 FAMILY 20.1.4 RTCVAL REGISTER MAPPINGS YEAR: YEAR VALUE REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-x, HSC YRTEN2 R/W-x, HSC YRTEN1 R/W-x, HSC YRTEN0 R/W-x, HSC YRONE3 R/W-x, HSC YRONE2 R/W-x, HSC YRONE1 R/W-x, HSC YRONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown REGISTER 20-4: U-0 -- bit 15 R/W-x, HSC YRTEN3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 bit 3-0 Unimplemented: Read as `0' YRTEN<3:0>: Binary Coded Decimal Value of Year's Tens Digit bits Contains a value from 0 to 9. YRONE<3:0>: Binary Coded Decimal Value of Year's Ones Digit bits Contains a value from 0 to 9. A write to the YEAR register is only allowed when RTCWREN = 1. Note 1: REGISTER 20-5: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 -- U-0 -- R/W-x, HSC MTHTEN0 R/W-x, HSC MTHONE3 R/W-x, HSC MTHONE2 R/W-x, HSC MTHONE1 R/W-x, HSC MTHONE0 bit 8 U-0 -- R/W-x, HSC DAYTEN1 R/W-x, HSC DAYTEN0 R/W-x, HSC DAYONE3 R/W-x, HSC DAYONE2 R/W-x, HSC DAYONE1 R/W-x, HSC DAYONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit bit Contains a value of 0 or 1. MTHONE<3:0>: Binary Coded Decimal Value of Month's Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as `0' DAYTEN<1:0>: Binary Coded Decimal Value of Day's Tens Digit bits Contains a value from 0 to 3. DAYONE<3:0>: Binary Coded Decimal Value of Day's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: DS39969B-page 290 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 20-6: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x, HSC HRTEN1 R/W-x, HSC HRTEN0 R/W-x, HSC HRONE3 R/W-x, HSC HRONE2 R/W-x, HSC HRONE1 WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- R/W-x, HSC WDAY2 R/W-x, HSC WDAY1 R/W-x, HSC WDAY0 bit 8 R/W-x, HSC HRONE0 bit 0 Unimplemented: Read as `0' WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Unimplemented: Read as `0' HRTEN<1:0>: Binary Coded Decimal Value of Hour's Tens Digit bits Contains a value from 0 to 2. HRONE<3:0>: Binary Coded Decimal Value of Hour's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 20-7: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 MINSEC: MINUTES AND SECONDS VALUE REGISTER R/W-x, HSC MINTEN1 R/W-x, HSC MINTEN0 R/W-x, HSC MINONE3 R/W-x, HSC MINONE2 R/W-x, HSC MINONE1 R/W-x, HSC MINONE0 bit 8 R/W-x, HSC MINTEN2 R/W-x, HSC SECTEN2 R/W-x, HSC SECTEN1 R/W-x, HSC SECTEN0 R/W-x, HSC SECONE3 R/W-x, HSC SECONE2 R/W-x, HSC SECONE1 R/W-x, HSC SECONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' MINTEN<2:0>: Binary Coded Decimal Value of Minute's Tens Digit bits Contains a value from 0 to 5. MINONE<3:0>: Binary Coded Decimal Value of Minute's Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as `0' SECTEN<2:0>: Binary Coded Decimal Value of Second's Tens Digit bits Contains a value from 0 to 5. SECONE<3:0>: Binary Coded Decimal Value of Second's Ones Digit bits Contains a value from 0 to 9. 2010 Microchip Technology Inc. DS39969B-page 291 PIC24FJ256DA210 FAMILY 20.1.5 ALRMVAL REGISTER MAPPINGS ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 -- U-0 -- R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 8 U-0 -- R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0 REGISTER 20-8: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit bit Contains a value of 0 or 1. MTHONE<3:0>: Binary Coded Decimal Value of Month's Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as `0' DAYTEN<1:0>: Binary Coded Decimal Value of Day's Tens Digit bits Contains a value from 0 to 3. DAYONE<3:0>: Binary Coded Decimal Value of Day's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: DS39969B-page 292 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 20-9: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 -- U-0 -- U-0 -- U-0 -- R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 8 R/W-x HRONE0 bit 0 Unimplemented: Read as `0' WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Unimplemented: Read as `0' HRTEN<1:0>: Binary Coded Decimal Value of Hour's Tens Digit bits Contains a value from 0 to 2. HRONE<3:0>: Binary Coded Decimal Value of Hour's Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 20-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x MINTEN2 R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 8 R/W-x SECONE0 bit 0 Unimplemented: Read as `0' MINTEN<2:0>: Binary Coded Decimal Value of Minute's Tens Digit bits Contains a value from 0 to 5. MINONE<3:0>: Binary Coded Decimal Value of Minute's Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as `0' SECTEN<2:0>: Binary Coded Decimal Value of Second's Tens Digit bits Contains a value from 0 to 5. SECONE<3:0>: Binary Coded Decimal Value of Second's Ones Digit bits Contains a value from 0 to 9. 2010 Microchip Technology Inc. DS39969B-page 293 PIC24FJ256DA210 FAMILY 20.2 Calibration 20.3 Alarm The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses for one minute and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute. Refer to the following steps for RTCC calibration: 1. Using another timer resource on the device, the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute and loaded into the RCFGCAL register. * Configurable from half second to one year * Enabled using the ALRMEN bit (ALCFGRPT<15>, Register 20-3) * One-time alarm and repeat alarm options available 20.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVAL should only take place when ALRMEN = 0. As shown in Figure 20-2, the interval selection of the alarm is configured through the AMASK bits (ALCFGRPT<13:10>). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs, once the alarm is enabled, is stored in the ARPT bits, ARPT<7:0> (ALCFGRPT<7:0>). When the value of the ARPT bits equals 00h and the CHIME bit (ALCFGRPT<14>) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading ARPT<7:0> with FFh. After each alarm is issued, the value of the ARPT bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the alarm will turn off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of the ARPT bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set. 2. EQUATION 20-1: RTCC CALIBRATION Error (clocks per minute) = (Ideal Frequency - Measured Frequency) x 60 Ideal Frequency = 32,768H 3. a) If the oscillator is faster then ideal (negative result form Step 2), the RCFGCAL register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. b) If the oscillator is slower then ideal (positive result from Step 2), the RCFGCAL register value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter, once every minute. 4. Divide the number of error clocks per minute by 4 to get the correct CAL value and load the RCFGCAL register with the correct value. (Each 1-bit increment in CAL adds or subtracts 4 pulses). Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off or immediately after the rising edge of the seconds pulse. Note: It is up to the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging. 20.3.2 ALARM INTERRUPT At every alarm event, an interrupt is generated. In addition, an alarm pulse output is provided that operates at half the frequency of the alarm. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. Note: Changing any of the registers, other then the RCFGCAL and ALCFGRPT registers and the CHIME bit while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. DS39969B-page 294 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 20-2: ALARM MASK SETTINGS Day of the Week Alarm Mask Setting (AMASK<3:0>) 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds 0011 - Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month 1001 - Every year(1) Note 1: s m m m s s s s s s Month Day Hours Minutes Seconds h d d m m d d d h h h h h h h m m m m m m m m s s s s s s s s Annually, except when configured for February 29. 2010 Microchip Technology Inc. DS39969B-page 295 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 296 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 21.0 32-BIT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 41. "32-Bit Programmable Cyclic Redundancy Check (CRC)" (DS39729). The information in this data sheet supersedes the information in the FRM. The 32-bit programmable CRC generator provides a hardware implemented method of quickly generating checksums for various networking and security applications. It offers the following features: * User-programmable CRC polynomial equation, up to 32 bits * Programmable shift direction (little or big-endian) * Independent data and polynomial lengths * Configurable interrupt output * Data FIFO Figure 21-1 displays a simplified block diagram of the CRC generator. A simple version of the CRC shift engine is displayed in Figure 21-2. Note: FIGURE 21-1: CRCDATH CRC BLOCK DIAGRAM CRCDATL Variable FIFO (4x32, 8x16 or 16x8) CRCWDATH LENDIAN Shift Buffer 1 FIFO Empty Event CRCWDATL CRCISEL 1 0 CRC Interrupt CRC Shift Engine 0 Shift Complete Event Shifter Clock 2 * FCY FIGURE 21-2: CRC SHIFT ENGINE DETAIL CRCWDATH CRCWDATL CRC Shift Engine Read/ rite Bus W X0 Shift Buffer Data X1 Xn(1) Bit 0 Bit 1 Bit n(1) Note 1: n = PLEN<4:1> + 1. 2010 Microchip Technology Inc. DS39969B-page 297 PIC24FJ256DA210 FAMILY 21.1 21.1.1 User Interface POLYNOMIAL INTERFACE 21.1.2 DATA INTERFACE The CRC module can be programmed for CRC polynomials of up of up the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN<4:0> bits (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equation; functionally, this includes an XOR operation on the corresponding bit in the CRC engine. Clearing the bit disables the XOR. For example, consider two CRC polynomials, one a 16-bit and the other a 32-bit equation. The module incorporates a FIFO that works with a variable data width. Input data width can be configured to any value between one and 32 bits using the DWIDTH<4:0> bits (CRCCON2<12:8>). When the data width is greater than 15, the FIFO is four words deep. When the DWITDH bits are between 15 and 8, the FIFO is 8 words deep. When the DWIDTH bits are less than 8, the FIFO is 16 words deep. The data for which the CRC is to be calculated must first be written into the FIFO. Even if the data width is less than 8, the smallest data element that can be written into the FIFO is one byte. For example, if DWIDTH is five, then the size of the data is DWIDTH + 1 or six. The data is written as a whole byte; the two unused upper bits are ignored by the module. Once data is written into the MSb of the CRCDAT registers (that is, MSb as defined by the data width), the value of the VWORD<4:0> bits (CRCCON1<12:8>) increments by one. For example, if DWIDTH is 24, the VWORD bits will increment when bit 7 of CRCDATH is written. Therefore, CRCDATL must always be written to before CRCDATH. The CRC engine starts shifting data when the CRCGO bit is set and the value of VWORD is greater than zero. Each word is copied out of the FIFO into a buffer register, which decrements VWORD. The data is then shifted out of the buffer. The CRC engine continues shifting at a rate of two bits per instruction cycle, until VWORD reaches zero. This means that for a given data width, it takes half that number of instructions for each word to complete the calculation. For example, it takes 16 cycles to calculate the CRC for a single word of 32-bit data. When VWORD reaches the maximum value for the configured value of DWIDTH (4, 8 or 16), the CRCFUL bit becomes set. When VWORD reaches zero, the CRCMPT bit becomes set. The FIFO is emptied and the VWORD<4:0> bits are set to `00000' whenever CRCEN is `0'. At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. EQUATION 21-1: 16-BIT, 32-BIT CRC POLYNOMIALS X16 + X12 + X5 + 1 and X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 To program these polynomial into the CRC generator, set the register bits as shown in Table 21-1. Note that the appropriate positions are set to `1' to indicate they are used in the equation (for example, X26 and X23). The `0' bit required by the equation is always XORed; thus, X0 is a don't care. For a polynomial of length 32, it is assumed that the 32nd bit will be used. Therefore, the X<31:1> bits do not have the 32nd bit. TABLE 21-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS Bit Values 16-Bit Polynomial 01111 0000 0000 0000 0001 0001 0000 0010 000X 32-Bit Polynomial 11111 0000 0100 1100 0001 0001 1101 1011 011x CRC Control Bits PLEN<4:0> X<31:16> X<15:0> DS39969B-page 298 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 21.1.3 DATA SHIFT DIRECTION 3. The LENDIAN bit (CRCCON1<3>) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction the data is shifted into the engine. The result of the CRC calculation will still be a normal CRC result, not a reverse CRC result. Preload the FIFO by writing to the CRCDATL and CRCDATH registers until the CRCFUL bit is set or no data is left. Clear old results by writing 00h to CRCWDATL and CRCWDATH. The CRCWDAT registers can also be left unchanged to resume a previously halted calculation. Set the CRCGO bit to start calculation. Write remaining data into the FIFO as space becomes available. When the calculation completes, CRCGO is automatically cleared. An interrupt will be generated if CRCISEL = 1. Read CRCWDATL and CRCWDATH for the result of the calculation. 4. 5. 6. 7. 21.1.4 INTERRUPT OPERATION 8. The module generates an interrupt that is configurable by the user for either of two conditions. If CRCISEL is `0', an interrupt is generated when the VWORD<4:0> bits make a transition from a value of `1' to `0'. If CRCISEL is `1', an interrupt will be generated after the CRC operation finishes and the module sets the CRCGO bit to `0'. Manually setting CRCGO to `0' will not generate an interrupt. Note that when an interrupt occurs, the CRC calculation would not yet be complete. The module will still need (PLEN + 1)/2 clock cycles after the interrupt is generated until the CRC calculation is finished. There are eight registers used to control programmable CRC operation: * * * * * * * * CRCCON1 CRCCON2 CRCXORL CRCXORH CRCDATL CRCDATH CRCWDATL CRCWDATH 21.1.5 1. 2. TYPICAL OPERATION To use the module for a typical CRC calculation: Set the CRCEN bit to enable the module. Configure the module for desired operation: a) Program the desired polynomial using the CRCXORL and CRCXORH registers, and the PLEN<4:0> bits. b) Configure the data width and shift direction using the DWIDTH and LENDIAN bits. c) Select the desired interrupt mode using the CRCISEL bit. The CRCCON1 and CRCCON2 registers (Register 21-1 and Register 21-2) control the operation of the module and configure the various settings. The CRCXOR registers (Register 21-3 and Register 21-4) select the polynomial terms to be used in the CRC equation. The CRCDAT and CRCWDAT registers are each register pairs that serve as buffers for the double-word input data, and CRC processed output, respectively. 2010 Microchip Technology Inc. DS39969B-page 299 PIC24FJ256DA210 FAMILY REGISTER 21-1: R/W-0 CRCEN bit 15 R-0, HSC CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR HC = Hardware Cleared bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-1, HSC CRCMPT R/W-0 CRCISEL R/W-0, HC CRCGO R/W-0 LENDIAN U-0 -- U-0 -- U-0 -- bit 0 CRCCON1: CRC CONTROL 1 REGISTER U-0 -- R/W-0 CSIDL R-0, HSC VWORD4 R-0, HSC VWORD3 R-0, HSC VWORD2 R-0, HSC VWORD1 R-0, HSC VWORD0 bit 8 HSC = Hardware Settable/Clearable bit CRCEN: CRC Enable bit 1 = Enables module 0 = Disables module; all state machines, pointers and CRCWDAT/CRCDATH reset; other SFRs are NOT reset Unimplemented: Read as `0' CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<4:0> 7 or 16 when PLEN<4:0> 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; the final word of data is still shifting through the CRC 0 = Interrupt on shift is complete and results are ready CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter is turned off LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the CRC, starting with the LSb (little endian) 0 = Data word is shifted into the CRC, starting with the MSb (big endian) Unimplemented: Read as `0' bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0 DS39969B-page 300 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 21-2: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 PLEN4 R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 CRCCON2: CRC CONTROL 2 REGISTER U-0 -- U-0 -- R/W-0 DWIDTH4 R/W-0 DWIDTH3 R/W-0 DWIDTH2 R/W-0 DWIDTH1 R/W-0 DWIDTH0 bit 8 R/W-0 PLEN0 bit 0 Unimplemented: Read as `0' DWIDTH<4:0>: Data Word Width Configuration bits Configures the width of the data word (data word width - 1). Unimplemented: Read as `0' PLEN<4:0>: Polynomial Length Configuration bits Configures the length of the polynomial (polynomial length - 1). REGISTER 21-3: R/W-0 X15 bit 15 R/W-0 X7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 X13 R/W-0 X12 R/W-0 X11 R/W-0 X10 R/W-0 X9 R/W-0 X8 bit 8 X14 R/W-0 R/W-0 X6 R/W-0 X5 R/W-0 X4 R/W-0 X3 R/W-0 X2 R/W-0 X1 U-0 -- bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown X<15:1>: XOR of Polynomial Term xn Enable bits Unimplemented: Read as `0' 2010 Microchip Technology Inc. DS39969B-page 301 PIC24FJ256DA210 FAMILY REGISTER 21-4: R/W-0 X31 bit 15 R/W-0 X23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 X22 R/W-0 X21 R/W-0 X20 R/W-0 X19 R/W-0 X18 R/W-0 X17 CRCXORH: CRC XOR HIGH REGISTER R/W-0 X29 R/W-0 X28 R/W-0 X27 R/W-0 X26 R/W-0 X25 R/W-0 X24 bit 8 R/W-0 X16 bit 0 X30 R/W-0 X<31:16>: XOR of Polynomial Term xn Enable bits REGISTER 21-5: R/W-0 DATA15 bit 15 R/W-0 DATA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 CRCDATL: CRC DATA LOW REGISTER R/W-0 DATA13 R/W-0 DATA12 R/W-0 DATA11 R/W-0 DATA10 R/W-0 DATA9 R/W-0 DATA8 bit 8 R/W-0 DATA14 R/W-0 DATA6 R/W-0 DATA5 R/W-0 DATA4 R/W-0 DATA3 R/W-0 DATA2 R/W-0 DATA1 R/W-0 DATA0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DATA<15:0>: CRC Input Data bits Writing to this register fills the FIFO; reading from this register returns `0'. REGISTER 21-6: R/W-0 DATA15 bit 15 R/W-0 DATA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 CRCDATH: CRC DATA HIGH REGISTER R/W-0 DATA13 R/W-0 DATA12 R/W-0 DATA11 R/W-0 DATA10 R/W-0 DATA9 R/W-0 DATA8 bit 8 R/W-0 DATA14 R/W-0 DATA6 R/W-0 DATA5 R/W-0 DATA4 R/W-0 DATA3 R/W-0 DATA2 R/W-0 DATA1 R/W-0 DATA0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DATA<15:0>: CRC Input Data bits Writing to this register fills the FIFO; reading from this register returns `0'. DS39969B-page 302 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 21-7: R/W-0, HSC SDATA15 bit 15 R/W-0, HSC SDATA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0, HSC SDATA6 R/W-0, HSC SDATA5 R/W-0, HSC SDATA4 R/W-0, HSC SDATA3 R/W-0, HSC SDATA2 R/W-0, HSC SDATA1 CRCWDATL: CRC SHIFT LOW REGISTER R/W-0, HSC SDATA13 R/W-0, HSC SDATA12 R/W-0, HSC SDATA11 R/W-0, HSC SDATA10 R/W-0, HSC SDATA9 R/W-0, HSC SDATA8 bit 8 R/W-0, HSC SDATA0 bit 0 R/W-0, HSC SDATA14 SDATA<15:0>: CRC Shift Register bits Writing to this register writes to the CRC Shift register through the CRC write bus. Reading from this register reads the CRC read bus. REGISTER 21-8: R/W-0, HSC SDATA31 bit 15 R/W-0, HSC SDATA23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 CRCWDATH: CRC SHIFT HIGH REGISTER R/W-0, HSC SDATA29 R/W-0, HSC SDATA28 R/W-0, HSC SDATA27 R/W-0, HSC SDATA26 R/W-0, HSC SDATA25 R/W-0, HSC SDATA24 bit 8 R/W-0, HSC SDATA30 R/W-0, HSC SDATA22 R/W-0, HSC SDATA21 R/W-0, HSC SDATA20 R/W-0, HSC SDATA19 R/W-0, HSC SDATA18 R/W-0, HSC SDATA17 R/W-0, HSC SDATA16 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SDATA<31:16>: CRC Input Data bits Writing to this register writes to the CRC Shift register through the CRC write bus. Reading from this register reads the CRC read bus. 2010 Microchip Technology Inc. DS39969B-page 303 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 304 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 22.0 Note: GRAPHICS CONTROLLER MODULE (GFX) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 43. "Graphics Controller Module (GFX)" (DS39731). The information in this data sheet supersedes the information in the FRM. Key features of the GFX module include: * Direct interface to three categories of display glasses: - Monochrome STN - Color STN - Color TFT * Programmable vertical and horizontal synchronization signals' timing and display clock frequency to meet display's frame rates * Optional internal or external display buffer to accommodate different types of display resolution * Graphic hardware accelerators: - Character Graphics Processing Unit (CHRGPU) - Rectangle Copy Graphics Processing Unit (RCCGPU) - Inflate Processing Unit (IPU) * 256 Entries Color Look-up Table (CLUT) * Supports 1/2/4/8/16 bits-per-pixel (bpp) color depth * Programmable display resolution * Supports multiple display interfaces: - 4/8/16-bit Monochrome STN - 4/8/16-bit Color STN - 9/12/18/24-bit color TFT (18 and 24-bit displays are connected as 16-bit 5-6-5 RGB color format) The Graphics Controller (GFX) module is specifically designed to directly interface with the display glasses, with a built-in analog drive, to individually control pixels in the screen. The module also provides an accelerated rendering of vertical and horizontal lines, rectangles, copying of rectangular area between different locations on the screen, drawing texts and decompressing packed data. The use of the accelerated rendering is performed using command registers. Once initiated, the hardware will perform the rendering, and the software can either poll the status, or use the interrupts to continue rendering of the succeeding shapes. FIGURE 22-1: GRAPHICS MODULE OVERVIEW PIC24F Graphics Controller Module Display Interface Clock (DISPCLK) System Clock Registers and Control Interface Display Module Interface GD<15:0> VSYNC RCCGPU CHRGPU IPU GEN CLUT Memory Request Arbiter GPWR GCLK System RAM 2010 Microchip Technology Inc. DS39969B-page 305 To Display Glass Graphics Controller Clock (G1CLK) HSYNC GPU Command Interface PIC24FJ256DA210 FAMILY 22.1 GFX Module Registers G1CMDL: GPU COMMAND LOW REGISTER R/W-0 GCMD14 R/W-0 GCMD13 R/W-0 GCMD12 R/W-0 GCMD11 R/W-0 GCMD10 R/W-0 GCMD9 R/W-0 GCMD8 bit 8 R/W-0 GCMD6 R/W-0 GCMD5 R/W-0 GCMD4 R/W-0 GCMD3 R/W-0 GCMD2 R/W-0 GCMD1 R/W-0 GCMD0 bit 0 REGISTER 22-1: R/W-0 GCMD15 bit 15 R/W-0 GCMD7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown GCMD<15:0>: Low GPU Command bits The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). Writes to this register will not trigger the loading of GCMD <31:0> to the command FIFO. For command FIFO loading, see the G1CMDH register description. REGISTER 22-2: R/W-0 GCMD31 bit 15 R/W-0 GCMD23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 G1CMDH: GPU COMMAND HIGH REGISTER R/W-0 R/W-0 GCMD29 R/W-0 GCMD28 R/W-0 GCMD27 R/W-0 GCMD26 R/W-0 GCMD25 R/W-0 GCMD24 bit 8 R/W-0 R/W-0 GCMD21 R/W-0 GCMD20 R/W-0 GCMD19 R/W-0 GCMD18 R/W-0 GCMD17 R/W-0 GCMD16 bit 0 GCMD30 GCMD22 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown GCMD<31:16>: High GPU Command bits The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). A word write to the G1CMDH register triggers the loading of GCMD<31:0> to the command FIFO. Byte writes to the G1CMDH are allowed but only a high byte write will trigger the command loading to the FIFO. Low byte write to this register will only update the G1CMDH<7:0> bits. DS39969B-page 306 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-3: R/W-0 G1EN bit 15 R/W-0 PUBPP2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 PUBPP1 R/W-0 PUBPP0 R-0, HSC GCMDCNT4 R-0, HSC GCMDCNT3 R-0, HSC GCMDCNT2 R-0, HSC GCMDCNT1 U-0 -- G1CON1: DISPLAY CONTROL REGISTER 1 R/W-0 G1SIDL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R-0, HSC GCMDCNT0 bit 0 GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0 G1EN: Module Enable bit 1 = Display module is enabled 0 = Display module is disabled Unimplemented: Read as `0' G1SIDL: Stop in Idle bit 1 = Display module stops in Idle mode 0 = Display module does not stop in Idle mode GCMDWMK<4:0>: Command FIFO Watermark bits Sets the command watermark level that triggers the CMDLVIF interrupt and sets the CMDLV flag; GCMDWMK<4:0> (10000 = Reserved) 10000 = If the number of commands present in the FIFO goes from 16 to 15 commands, the CMDLVIF interrupt will trigger and the CMDLV flag will be set 01111 = f the number of commands present in the FIFO goes from 15 to 14 commands, CMDLVIF interrupt will trigger and CMDLV flag will be set . . . 00001 = If the number of commands present in the FIFO goes from 1 to 0 commands, the CMDLVIF interrupt will trigger and the CMDLV flag will be set 00000 = CMDLVIF interrupt will not trigger and the CMDLV flag will not be set PUBPP<2:0>: GPU bits-per-pixel (bpp) Setting bits Other = Reserved 100 = 16 bits-per-pixel 011 = 8 bits-per-pixel 010 = 4 bits-per-pixel 001 = 2 bits-per -pixel 000 = 1-bit -per-pixel GCMDCNT<4:0>: Command FIFO Occupancy Status bits When the FIFO is full, any additional commands written to the FIFO are discarded. 10000 = 16 commands are present in the FIFO 01111 = 15 commands are present in the FIFO . . . 0001 = 1 command is present in the FIFO 0000 = 0 command is present in the FIFO bit 14 bit 13 bit 12-8 bit 7-5 bit 4-0 2010 Microchip Technology Inc. DS39969B-page 307 PIC24FJ256DA210 FAMILY REGISTER 22-4: R/W-0 DPGWDTH1 bit 15 R/W-0 DPBPP2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DPBPP1 R/W-0 DPBPP0 U-0 -- U-0 -- R/W-0 DPMODE2 R/W-0 DPMODE1 G1CON2: DISPLAY CONTROL REGISTER 2 R/W-0 R/W-0 DPSTGER1 R/W-0 DPSTGER0 U-0 -- U-0 -- R/W-0 DPTEST1 R/W-0 DPTEST0 bit 8 R/W-0 DPMODE0 bit 0 DPGWDTH0 DPGWDTH<1:0>: STN Display Glass Data Width bits 11 = Reserved 10 = 16 bits wide 01 = 8 bits wide 00 = 4 bits wide These bits have no effect on TFT mode. TFT display glass data width is always assumed to be 16 bits wide. DPSTGER<1:0>: Display Data Timing Stagger bits 11 = Delays of the display data are staggered in groups: Bit group 0: 0 4 8 12 - not delayed Bit group 1: 1 5 9 13 - delayed by 1/2 GPUCLK cycle Bit group 2: 2 6 10 14 - delayed by full GPUCLK cycle Bit group 3: 3 7 11 15 - delayed by 1 1/2 GPUCLK cycle 10 = Even bits of the display data are delayed by 1 full GPUCLK cycle; odd bits are not delayed 01 = Odd bits of the display data are delayed by 1/2 GPUCLK cycle; even bits are not delayed 00 = Display data timing is all synchronized on one clock GPUCLK edge Unimplemented: Read as `0' DPTEST<1:0>: Display Test Pattern Generator bits 11 = Borders 10 = Bars 01 = Black screen 00 = Normal Display mode; test patterns are off DPBPP<2:0>: Display bits-per-pixel Setting bits This setting must match the GPU bits-per-pixel set in PUBPP<2:0> (G1CON1<7:5>). 100 = 16 bits-per-pixel 011 = 8 bits-per-pixel 010 = 4 bits-per-pixel 001 = 2 bits-per-pixel 000 = 1 bit-per-pixel Other = Reserved Unimplemented: Read as `0' DPMODE<2:0>: Display Glass Type bits 011 = Color STN type 010 = Mono STN type 001 = TFT type 000 = Display off Other = Reserved bit 13-12 bit 11-10 bit 9-8 bit 7-5 bit 4-3 bit 2-0 DS39969B-page 308 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-5: U-0 -- bit 15 R/W-0 DPCLKPOL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DPENPOL R/W-0 DPVSPOL R/W-0 DPHSPOL R/W-0 DPPWROE R/W-0 DPENOE R/W-0 DPVSOE G1CON3: DISPLAY CONTROL REGISTER 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DPPINOE R/W-0 DPPOWER bit 8 R/W-0 DPHSOE bit 0 Unimplemented: Read as `0' DPPINOE: Display Pin Output Pad Enable bit DPPINOE is the master output enable and must be set to allow GDBEN<15:0>, DPENOE, DPPWROE, DPVSOE and DPHSOE to enable the associated pads 1 = Enable display output pads 0 = Disable display output signals as set by GDBEN<15:0> Pins used by the signals are assigned to the next enabled module that uses the same pins. For data signals, GDBEN<15:0> can be used to disable or enable specific data signals while DPPINOE is set. DPPOWER: Display Power-up Power-Down Sequencer Control bit Refer to the "PIC24F Family Reference Manual", Section 43. "Graphics Controller Module (GFX)" for details. 1 = Set Display Power Sequencer Control port (GPWR) to `1' 0 = Set Power Control Sequencer signal (GPWR) `0' DPCLKPOL: Display Glass Clock (GCLK) Polarity bit 1 = Display latches data on the positive edge of GCLK 0 = Display latches data on the negative edge of GCLK DPENPOL: Display Enable Signal (GEN) Polarity bit For TFT mode (DPMODE (G1CON2<2:0>) = 001): 1 = Active-high (GEN) 0 = Active-low (GEN) For STN mode (DPMODE (G1CON2<2:0>) = 010 or 011): 1 = GEN connects to the shift clock input of the display (Shift Clock mode) 0 = GEN connects to the MOD input of the display (Line/Frame Toggle mode) DPVSPOL: Display Vertical Synchronization (VSYNC) Polarity bit 1 = Active-high (VSYNC) 0 = Active-low (VSYNC) DPHSPOL: Display Horizontal Synchronization (HSYNC) Polarity bit 1 = Active-high (HSYNC) 0 = Active-low (HSYNC) DPPWROE: Display Power-up/Power-Down Sequencer Control port (GPWR) enable bit 1 = GPWR port is enabled (pin controlled by the DPPOWER bit (G1CON3<8>)) 0 = GPWR port is disabled (pin can be used as an ordinary I/O) DPENOE: Display Enable Port Enable bit 1 = GEN port is enabled 0 = GEN port is disabled bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 2010 Microchip Technology Inc. DS39969B-page 309 PIC24FJ256DA210 FAMILY REGISTER 22-5: bit 1 G1CON3: DISPLAY CONTROL REGISTER 3 (CONTINUED) DPVSOE: Display Vertical Synchronization Port Enable bit 1 = VSYNC port is enabled 0 = VSYNC port is disabled DPHSOE: Display Horizontal Synchronization Port Enable bit 1 = HSYNC port is enabled 0 = HSYNC port is disabled bit 0 REGISTER 22-6: R-0, HSC PUBUSY bit 15 R-0, HSC IPUBUSY bit 7 Legend: R = Readable bit -n = Value at POR bit 15 -- G1STAT: GFX STATUS REGISTER U-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R-0, HSC RCCBUSY R-0, HSC CHRBUSY R-0, HSC VMRGN R-0, HSC HMRGN R-0, HSC CMDLV R-0, HSC CMDFUL R-0, HSC CMDMPT bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PUBUSY: Processing Units are Busy Status bit This bit is logically equivalent to the ORed combination of IPUBUSY, RCCBUSY or CHRBUSY. 1 = At least one processing unit is busy 0 = None of the processing units are busy Unimplemented: Read as `0' IPUBUSY: Inflate Processing Unit Busy Status bit 1 = IPU is busy 0 = IPU is not busy RCCBUSY: Rectangle Copy Graphics Processing Unit Busy Status bit 1 = RCCGPU is busy 0 = RCCGPU is not busy CHRBUSY: Character Graphics Processing Unit Busy Status bit 1 = CHRGPU is busy 0 = CHRGPU is not busy VMRGN: Vertical Blanking Status bit 1 = Display interface is in the vertical blanking period 0 = Display interface is not in the vertical blanking period HMRGN: Horizontal Blanking Status bit 1 = Display interface is in the horizontal blanking period 0 = Display interface is not in the horizontal blanking period CMDLV: Command Watermark Level Status bit The number of commands in the command FIFO changed from equal (=) to the command watermark value to less than (<) the Command Watermark value set in CMDWMK (G1CON1<12:8>) register bits. 1 = Command in FIFO is less than the set CMDWMK value 0 = Command in FIFO is equal to or greater than the set CMDWMK value CMDFUL: Command FIFO Full Status bit 1 = Command FIFO is full 0 = Command FIFO is not full CMDMPT: Command FIFO Empty Status bit 1 = Command FIFO is empty 0 = Command FIFO is not empty bit 14-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39969B-page 310 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-7: R/W-0 PUIE bit 15 R/W-0 IPUIE bit 7 G1IE: GFX INTERRUPT ENABLE REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 RCCIE R/W-0 CHRIE R/W-0 VMRGNIE R/W-0 HMRGNIE R/W-0 CMDLVIE R/W-0 CMDFULIE R/W-0 CMDMPTIE bit 0 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 14-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PUIE: Processing Units Complete Interrupt Enable bit 1 = Enables the PU complete interrupt 0 = Disables the PU complete interrupt Unimplemented: Read as `0' IPUIE: Inflate Processing Unit Complete Interrupt Enable bit 1 = Enables the IPU complete interrupt 0 = Disables the IPU complete interrupt RCCIE: Rectangle Copy Graphics Processing Unit Complete Interrupt bit 1 = Enables the RCCGPU complete interrupt 0 = Disables the RCCGPU complete interrupt CHRIE: Character Graphics Processing Unit Busy Interrupt bit 1 = Enables the CHRGPU busy interrupt 0 = Disables the CHRGPU busy interrupt VMRGNIE: Vertical Blanking Interrupt Enable bit 1 = Enables the vertical blanking period interrupt 0 = Disables the vertical blanking period interrupt HMRGNIE: Horizontal Blanking Interrupt Enable bit 1 = Enables the horizontal blanking period interrupt 0 = Disables the horizontal blanking period interrupt CMDLVIE: Command Watermark Interrupt Enable bit 1 = Enables the command watermark interrupt bit 0 = Disables the command watermark interrupt bit CMDFULIE: Command FIFO Full Interrupt Enable bit 1 = Enables the command FIFO full interrupt 0 = Disables the command FIFO full interrupt CMDMPTIE: Command FIFO Empty Interrupt Enable bit 1 = Enables the command FIFO empty interrupt 0 = Disables the command FIFO empty interrupt 2010 Microchip Technology Inc. DS39969B-page 311 PIC24FJ256DA210 FAMILY REGISTER 22-8: R/W-0, HS PUIF bit 15 U-0 -- G1IR: GFX INTERRUPT STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0, HS CHRIF(1) R/W-0, HS VMRGNIF R/W-0, HS HMRGNIF R/W-0, HS CMDLVIF R/W-0, HS CMDFULIF R/W-0, HS CMDMPTIF bit 0 R/W-0, HS R/W-0, HS IPUIF(1) RCCIF(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 14-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PUIF: Processing Units Complete Interrupt Flag bit PUIF is an ORed combination of IPUIF, RCCIF and CHRIF. 1 = One or more PUs completed command execution (must be cleared in software) 0 = All PUs are Idle or busy completing command execution Unimplemented: Read as `0' IPUIF: Inflate Processing Unit Complete Interrupt Flag bit(1) 1 = IPU completed command execution (must be cleared in software) 0 = IPU is Idle or busy completing command execution RCCIF: Rectangle Copy Graphics Processing Unit Complete Interrupt Flag bit(1) 1 = RCCGPU completed command execution (must be cleared in software) 0 = RCCGPU is Idle or busy completing command execution CHRIF: Character Graphics Processing Unit Complete Interrupt Flag bit(1) 1 = CHRGPU completed command execution (must be cleared in software) 0 = CHRGPU is Idle or busy completing command execution VMRGNIF: Vertical Blanking Interrupt Flag bit 1 = Display interface is in the vertical blanking period (must be cleared in software) 0 = Display interface is not in the vertical blanking period HMRGNIF: Horizontal Blanking Interrupt Flag bit 1 = Display interface is in the horizontal blanking period (must be cleared in software) 0 = Display interface is not in the horizontal blanking period CMDLVIF: Command Watermark Interrupt Flag bit 1 = Command watermark level is reached (must be cleared in software) 0 = Command watermark level is not yet reached CMDFULIF: Command FIFO Full Interrupt Flag bit 1 = Command FIFO is full (must be cleared in software) 0 = Command FIFO is not full CMDMPTIF: Command FIFO Empty Interrupt Flag bit 1 = Command FIFO is empty (must be cleared in software) 0 = Command FIFO is not empty The logic of each Processing Unit Status bit is the reverse of the PUIF. This provides flexibility on software code utilizing the processing units. Note 1: DS39969B-page 312 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-9: R/W-0 W1ADR15 bit 15 R/W-0 W1ADR7 bit 7 G1W1ADRL: GPU WORK AREA 1 START ADDRESS REGISTER LOW R/W-0 W1ADR13 R/W-0 W1ADR12 R/W-0 W1ADR11 R/W-0 W1ADR10 R/W-0 W1ADR9 R/W-0 W1ADR8 bit 8 R/W-0 W1ADR0 bit 0 R/W-0 W1ADR14 R/W-0 W1ADR6 R/W-0 W1ADR5 R/W-0 W1ADR4 R/W-0 W1ADR3 R/W-0 W1ADR2 R/W-0 W1ADR1 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown W1ADR<15:0>: GPU Work Area 1 Start Address Low bits Work area address must point to an even byte address in memory. REGISTER 22-10: G1W1ADRH: GPU WORK AREA 1 START ADDRESS REGISTER HIGH U-0 -- bit 15 R/W-0 W1ADR23 bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 W1ADR22 R/W-0 W1ADR21 R/W-0 W1ADR20 R/W-0 W1ADR19 R/W-0 W1ADR18 R/W-0 W1ADR17 R/W-0 W1ADR16 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' W1ADR<23:16>: GPU Work Area 1 Start Address High bits Work area address must point to an even byte address in memory. REGISTER 22-11: G1W2ADRL: GPU WORK AREA 2 START ADDRESS REGISTER LOW R/W-0 W2ADR15 bit 15 R/W-0 W2ADR7 bit 7 R/W-0 W2ADR14 R/W-0 W2ADR13 R/W-0 W2ADR12 R/W-0 W2ADR11 R/W-0 W2ADR10 R/W-0 W2ADR9 R/W-0 W2ADR8 bit 8 R/W-0 W2ADR0 bit 0 R/W-0 W2ADR6 R/W-0 W2ADR5 R/W-0 W2ADR4 R/W-0 W2ADR3 R/W-0 W2ADR2 R/W-0 W2ADR1 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown W2ADR<15:0>: GPU Work Area 2 Start Address Low bits Work area address must point to an even byte address in memory. 2010 Microchip Technology Inc. DS39969B-page 313 PIC24FJ256DA210 FAMILY REGISTER 22-12: G1W2ADRH: GPU WORK AREA 2 START ADDRESS REGISTER HIGH U-0 -- bit 15 R/W-0 W2ADR23 bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 W2ADR16 bit 0 R/W-0 W2ADR22 R/W-0 W2ADR21 R/W-0 W2ADR20 R/W-0 W2ADR19 R/W-0 W2ADR18 R/W-0 W2ADR17 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' W2ADR<23:16>: GPU Work Area 2 Start Address High bits Work area address must point to an even byte address in memory. REGISTER 22-13: G1PUW: GPU WORK AREA WIDTH REGISTER U-0 -- bit 15 R/W-0 PUW7 bit 7 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PUW10 R/W-0 PUW9 R/W-0 PUW8 bit 8 R/W-0 PUW0 bit 0 R/W-0 PUW6 R/W-0 PUW5 R/W-0 PUW4 R/W-0 PUW3 R/W-0 PUW2 R/W-0 PUW1 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' PUW<10:0>: GPU Work Area Width bits (in pixels) REGISTER 22-14: G1PUH: GPU WORK AREA HEIGHT REGISTER U-0 -- bit 15 R/W-0 PUH7 bit 7 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PUH10 R/W-0 PUH9 R/W-0 PUH8 bit 8 R/W-0 PUH0 bit 0 R/W-0 PUH6 R/W-0 PUH5 R/W-0 PUH4 R/W-0 PUH3 R/W-0 PUH2 R/W-0 PUH1 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' PUH<10:0>: GPU Work Area Height bits (in pixels) DS39969B-page 314 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-15: G1DPADRL: DISPLAY BUFFER START ADDRESS REGISTER LOW R/W-0 DPADR15 bit 15 R/W-0 DPADR7 bit 7 R/W-0 DPADR14 R/W-0 DPADR13 R/W-0 DPADR12 R/W-0 DPADR11 R/W-0 DPADR10 R/W-0 DPADR9 R/W-0 DPADR8 bit 8 R/W-0 DPADR0 bit 0 R/W-0 DPADR6 R/W-0 DPADR5 R/W-0 DPADR4 R/W-0 DPADR3 R/W-0 DPADR2 R/W-0 DPADR1 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DPADR<15:0>: Display Buffer Start Address Low bits Display buffer start address must point to an even byte address in memory. REGISTER 22-16: G1DPADRH: DISPLAY BUFFER START ADDRESS REGISTER HIGH U-0 -- bit 15 R/W-0 DPADR23 bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 DPADR22 R/W-0 DPADR21 R/W-0 DPADR20 R/W-0 DPADR19 R/W-0 DPADR18 R/W-0 DPADR17 R/W-0 DPADR16 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' DPADR<23:16>: Display Buffer Start Address High bits Display buffer start address must point to an even byte address in memory. REGISTER 22-17: G1DPW: DISPLAY BUFFER WIDTH REGISTER U-0 -- bit 15 R/W-0 DPW7 bit 7 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DPW10 R/W-0 DPW9 R/W-0 DPW8 bit 8 R/W-0 DPW0 bit 0 R/W-0 DPW6 R/W-0 DPW5 R/W-0 DPW4 R/W-0 DPW3 R/W-0 DPW2 R/W-0 DPW1 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' DPW<10:0>: Display Frame Width bits (in pixels) 2010 Microchip Technology Inc. DS39969B-page 315 PIC24FJ256DA210 FAMILY REGISTER 22-18: G1DPH: DISPLAY BUFFER HEIGHT REGISTER U-0 -- bit 15 R/W-0 DPH7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-0 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DPH10 R/W-0 DPH9 R/W-0 DPH8 bit 8 R/W-0 DPH0 bit 0 R/W-0 DPH6 R/W-0 DPH5 R/W-0 DPH4 R/W-0 DPH3 R/W-0 DPH2 R/W-0 DPH1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' DPH<10:0>: Display Frame Height bits (in pixels) REGISTER 22-19: G1DPWT: DISPLAY TOTAL WIDTH REGISTER U-0 -- bit 15 R/W-0 DPWT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DPWT6 R/W-0 DPWT5 R/W-0 DPWT4 R/W-0 DPWT3 R/W-0 DPWT2 R/W-0 DPWT1 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DPWT10 R/W-0 DPWT9 R/W-0 DPWT8 bit 8 R/W-0 DPWT0 bit 0 Unimplemented: Read as `0' DPWT<10:0>: Display Total Width bits (in pixels) REGISTER 22-20: G1DPHT: DISPLAY TOTAL HEIGHT REGISTER U-0 -- bit 15 R/W-0 DPHT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 DPHT6 R/W-0 DPHT5 R/W-0 DPHT4 R/W-0 DPHT3 R/W-0 DPHT2 R/W-0 DPHT1 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 DPHT10 R/W-0 DPHT9 R/W-0 DPHT8 bit 8 R/W-0 DPHT0 bit 0 Unimplemented: Read as `0' DPHT<10:0>: Display Total Height bits (in pixels) DS39969B-page 316 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-21: G1ACTDA: ACTIVE DISPLAY AREA REGISTER R/W-0 ACTLINE7 bit 15 R/W-0 ACTPIX7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ACTPIX6 R/W-0 ACTPIX5 R/W-0 ACTPIX4 R/W-0 ACTPIX3 R/W-0 ACTPIX2 R/W-0 ACTPIX1 R/W-0 ACTLINE6 R/W-0 ACTLINE5 R/W-0 ACTLINE4 R/W-0 ACTLINE3 R/W-0 ACTLINE2 R/W-0 ACTLINE1 R/W-0 ACTLINE0 bit 8 R/W-0 ACTPIX0 bit 0 ACTLINE<7:0>: Number of Lines Before the First Active (Displayed) Line bits Typically, ACTLINEx = VENSTx (G1DBLCON<15:8>). This register is added for versatility in the timing of the active lines. For TFT mode, DPMODE bits (G1CON2<2:0>) = 001; the minimum value is 2. For STN mode, DPMODE bits (G1CON2<2:0>) = 010,011,100; the minimum value is 0. ACTPIX<7:0>: Number of Pixels Before the First Active (Displayed) Pixel bits (in DISPCLKs) Typically, ACTPIXx = HENSTx (G1DBLCON<7:0>). This register is added for versatility in the timing of the active pixels. Note that the programmed value is computed in DISPCLK cycles. This value is dependent on the DPGWDTH bit (G1CON2<15:14>). Refer to the "PIC24F Family Reference Manual", Section 43. "Graphics Controller Module (GFX)" for details. bit 7-0 REGISTER 22-22: G1HSYNC: HORIZONTAL SYNCHRONIZATION CONTROL REGISTER R/W-0 HSLEN7 bit 15 R/W-0 HSST7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 HSST6 R/W-0 HSST5 R/W-0 HSST4 R/W-0 HSST3 R/W-0 HSST2 R/W-0 HSST1 R/W-0 HSLEN6 R/W-0 HSLEN5 R/W-0 HSLEN4 R/W-0 HSLEN3 R/W-0 HSLEN2 R/W-0 HSLEN1 R/W-0 HSLEN0 bit 8 R/W-0 HSST0 bit 0 HSLEN<7:0>: HSYNC Pulse-Width Configuration bits (in DISPCLKs) DPHSOE bit (G1CON3<0>) must be set for the HSYNC signal to toggle; minimum value is 1. HSST<7:0>: HSYNC Start Delay Configuration bits (in DISPCLKs) This is the number of DISPCLK cycles from the start of horizontal blanking to the start of HSYNC active. 2010 Microchip Technology Inc. DS39969B-page 317 PIC24FJ256DA210 FAMILY REGISTER 22-23: G1VSYNC: VERTICAL SYNCHRONIZATION CONTROL REGISTER R/W-0 VSLEN7 bit 15 R/W-0 VSST7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 VSST6 R/W-0 VSST5 R/W-0 VSST4 R/W-0 VSST3 R/W-0 VSST2 R/W-0 VSST1 R/W-0 VSLEN6 R/W-0 VSLEN5 R/W-0 VSLEN4 R/W-0 VSLEN3 R/W-0 VSLEN2 R/W-0 VSLEN1 R/W-0 VSLEN0 bit 8 R/W-0 VSST0 bit 0 VSLEN<7:0>: VSYNC Pulse-Width Configuration bits (in lines) The DPVSOE bit (G1CON3<1>) must be set for the VSYNC signal to toggle; minimum value is 1. VSST<7:0>: VSYNC Start Delay Configuration bits (in lines) This is the number of lines from the start of vertical blanking to the start of VSYNC active. REGISTER 22-24: G1DBLCON: DISPLAY BLANKING CONTROL REGISTER R/W-0 VENST7 bit 15 R/W-0 HENST7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 HENST6 R/W-0 HENST5 R/W-0 HENST4 R/W-0 HENST3 R/W-0 HENST2 R/W-0 HENST1 R/W-0 VENST6 R/W-0 VENST5 R/W-0 VENST4 R/W-0 VENST3 R/W-0 VENST2 R/W-0 VENST1 R/W-0 VENST0 bit 8 R/W-0 HENST0 bit 0 VENST<7:0>: Vertical Blanking Start to First Displayed Line Configuration bits (in lines) This is the number of lines from the start of vertical blanking to the first displayed line of a frame. HENST<7:0>: Horizontal Blanking Start to First Displayed Pixel Configuration bits (in DISPCLKs) This is the number of GCLK cycles from the start of horizontal blanking to the first displayed pixel of each displayed line. DS39969B-page 318 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-25: G1CLUT: COLOR LOOK-UP TABLE CONTROL REGISTER R/W-0 CLUTEN bit 15 R/W-0 CLUTADR7 bit 7 R-0, HSC CLUTBUSY U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CLUTTRD R/W-0 CLUTRWEN bit 8 R/W-0 CLUTADR0 bit 0 R/W-0 CLUTADR6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLUTADR5 CLUTADR4 CLUTADR3 CLUTADR2 CLUTADR1 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 14 bit 13-10 bit 9 bit 8 bit 7-0 CLUTEN: Color Look-up Table Enable Control bit 1 = Color look-up table is enabled 0 = Color look-up table is disabled CLUTBUSY: Color Look-up Table Busy Status bit 1 = A CLUT entry read/write access is being executed 0 = No CLUT entry read/write access is being executed Unimplemented: Read as `0' CLUTTRD: Color Look-up Table Read Trigger bit Enabling this bit will trigger a read to the CLUT location determined by the CLUTADR bits (G1CLUT<7:0>) with CLUTRWEN enabled. 1 = CLUT read trigger is enabled (must be cleared in software after reading data in the G1CLUTRD register) 0 = CLUT read trigger is disabled CLUTRWEN: Color Look-up Table Read/Write Enable Control bit This bit must be set when reading or modifying entries on the CLUT and it must also be cleared when CLUT is used by the display controller. 1 = Color look-up table read/write enabled; display controller cannot access the CLUT 0 = Color look-up table read/write disabled; display controller can access the CLUT CLUTADR<7:0>: Color Look-up Table Memory Address bits 2010 Microchip Technology Inc. DS39969B-page 319 PIC24FJ256DA210 FAMILY REGISTER 22-26: G1CLUTWR: COLOR LOOK-UP TABLE (CLUT) MEMORY WRITE DATA REGISTER R/W-0 CLUTWR15 bit 15 R/W-0 CLUTWR7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CLUTWR6 R/W-0 CLUTWR5 R/W-0 CLUTWR4 R/W-0 CLUTWR3 R/W-0 CLUTWR2 R/W-0 CLUTWR1 R/W-0 CLUTWR14 R/W-0 CLUTWR13 R/W-0 CLUTWR12 R/W-0 CLUTWR11 R/W-0 CLUTWR10 R/W-0 CLUTWR9 R/W-0 CLUTWR8 bit 8 R/W-0 CLUTWR0 bit 0 CLUTWR<15:0>: Color Look-up Table Memory Write Data bits A write to this register triggers a write to the CLUT memory at the address pointed to by the CLUTADR bits. A word write or a high byte write to this register triggers a write to the CLUT memory at the address pointed to by CLUTADR. Low byte write to this register will only update the G1CLUTWR<7:0> and no write to CLUT memory will be triggered. During power-up and power-down of the display, the most recent data written to this register will be used to control the timing of the GPWR signal. Refer to the "PIC24F Family Reference Manual", Section 43. "Graphics Controller Module (GFX)" for details on writing entries to the CLUT. REGISTER 22-27: G1CLUTRD: COLOR LOOK-UP TABLE (CLUT) MEMORY READ DATA REGISTER R-0, HSC CLUTRD15 bit 15 R-0, HSC CLUTRD7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0, HSC CLUTRD6 R-0, HSC CLUTRD5 R-0, HSC CLUTRD4 R-0, HSC CLUTRD3 R-0, HSC CLUTRD2 R-0, HSC CLUTRD1 R-0, HSC CLUTRD14 R-0, HSC CLUTRD13 R-0, HSC CLUTRD12 R-0, HSC CLUTRD11 R-0, HSC CLUTRD10 R-0, HSC CLUTRD9 R-0, HSC CLUTRD8 bit 8 R-0, HSC CLUTRD0 bit 0 CLUTRD<15:0>: Color Look-up Table Memory Read Data bits This register contains the most recent read from the CLUT memory pointed to by the CLUTADR bits (G1CLUT<7:0>). Reading of the CLUT memory is triggered when the CLUTTRD bit (G1CLUT<9>) goes from `0' to `1'. Refer to the "PIC24F Family Reference Manual", Section 43. "Graphics Controller Module (GFX)" for details on reading entries from the CLUT. DS39969B-page 320 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-28: G1MRGN: INTERRUPT ADVANCE REGISTER R/W-0 VBAMGN7 bit 15 R/W-0 HBAMGN7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 HBAMGN6 R/W-0 HBAMGN5 R/W-0 HBAMGN4 R/W-0 HBAMGN3 R/W-0 R/W-0 R/W-0 VBAMGN6 R/W-0 VBAMGN5 R/W-0 VBAMGN4 R/W-0 VBAMGN3 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 VBAMGN2 VBAMGN1 VBAMGN0 HBAMGN2 HBAMGN1 HBAMGN0 VBAMGN<7:0>: Vertical Blanking Advance bits The number of DISPCLK cycles in advance that the vertical blanking interrupt will assert ahead of the actual start of the vertical blanking. HBAMGN<7:0>: Horizontal Blanking Advance bits The number of DISPCLK cycles in advance that the horizontal blanking interrupt will assert ahead of the actual start of the horizontal blanking. bit 7-0 REGISTER 22-29: G1CHRX: CHARACTER-X COORDINATE PRINT POSITION REGISTER U-0 -- bit 15 R-0, HSC bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CURPOSX2 R-0, HSC CURPOSX1 U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC CURPOSX10 R-0, HSC CURPOSX9 R-0, HSC CURPOSX8 bit 8 R-0, HSC CURPOSX0 bit 0 CURPOSX7 CURPOSX6 CURPOSX5 CURPOSX4 CURPOSX3 Unimplemented: Read as `0' CURPOSX<10:0>: Current Character Position in the X-Coordinate bits 2010 Microchip Technology Inc. DS39969B-page 321 PIC24FJ256DA210 FAMILY REGISTER 22-30: G1CHRY: CHARACTER Y-COORDINATE PRINT POSITION REGISTER U-0 -- bit 15 R-0, HSC CURPOSY7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0, HSC CURPOSY6 R-0, HSC CURPOSY5 R-0, HSC CURPOSY4 R-0, HSC CURPOSY3 R-0, HSC CURPOSY2 R-0, HSC U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC R-0, HSC R-0, HSC bit 8 R-0, HSC bit 0 CURPOSY10 CURPOSY9 CURPOSY8 CURPOSY1 CURPOSY0 Unimplemented: Read as `0' CURPOSY<10:0>: Current Character Position in the Y-Coordinate bits REGISTER 22-31: G1IPU: INFLATE PROCESSOR STATUS REGISTER U-0 -- bit 15 U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 U-0 -- R-0, HSC R-0, HSC HUFFERR(2) BLCKERR(2) R-0, HSC LENERR(2) R-0, HSC R-0, HSC WRAPERR(2) IPUDONE(1,2) R-0, HSC BFINAL(1,2) bit 0 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5 HSC = Hardware Settable/Clearable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as `0' HUFFERR: Undefined Huffmann Code Encountered Status bit(2) 1 = Undefined code is encountered 0 = No undefined code is encountered BLCKERR: Undefined Block Code Encountered Status bit(2) 1 = Undefined block is encountered 0 = No undefined block is encountered LENERR: Mismatch in Expected Block Length Status bit(2) 1 = Mismatch in block length is detected 0 = No mismatch in block length is detected WRAPERR: Wrap-Around Error Status bit(2) 1 = Wrap-around error is encountered 0 = No wrap-around error is encountered IPUDONE: IPU Decompression Status bit(1,2) 1 = Decompression is done 0 = Decompression is not yet done BFINAL: Final Block Encountered Status bit(1,2) 1 = Final block is encountered 0 = Final block is not encountered IPUDONE and BFINAL status bits are set after successful decompression. All IPU status bits are available after each decompression. All status bits are automatically cleared every time a decompression command (IPU_DECOMPRESS) is issued. Note 1: 2: DS39969B-page 322 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-32: G1DBEN: DATA I/O PAD ENABLE REGISTER R/W-0 GDBEN15 bit 15 R/W-0 GDBEN7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 GDBEN6 R/W-0 GDBEN5 R/W-0 GDBEN4 R/W-0 GDBEN3 R/W-0 GDBEN2 R/W-0 GDBEN1 R/W-0 GDBEN14 R/W-0 GDBEN13 R/W-0 GDBEN12 R/W-0 GDBEN11 R/W-0 GDBEN10 R/W-0 GDBEN9 R/W-0 GDBEN8 bit 8 R/W-0 GDBEN0 bit 0 GDBEN<15:0>: Display Data Pads Output Enable bits 1 = Corresponding display data (GD 2010 Microchip Technology Inc. DS39969B-page 323 PIC24FJ256DA210 FAMILY 22.2 Display Resolution and Memory Requirements 22.4 Display Buffer and Work Areas Memory Locations The PIC24FJ256DA210 family of devices has two variants in terms of on-board RAM (24-Kbyte and 96-Kbyte variants). The 24-Kbyte variant supports monochrome displays while the 96-Kbyte variant supports Quarter VGA (QVGA) color displays, up to 256 colors. Support of higher resolution displays with higher color depth requirements are available by extending the data space through external memory. Table 22-1 provides the summary of image buffer memory requirements of different display resolutions and color depth requirements. 22.3 Display Clock (GCLK) Source Frequency of the Graphics Controller Display Clock (GCLK) signal is determined by programming the GCLKDIV bits (CLKDIV2<15:9>). For more information, refer to the "PIC24F Family Reference Manual", Section 6. "Oscillator" (DS39700). The PIC24FJ256DA210 family of devices has variants with two on-board RAM sizes. These are the 24-Kbyte and 96-Kbyte variants. These two RAM variants are further divided in terms of pin counts. The 100-pin count device will have the EPMP module available for extending RAM for applications. The 64-pin count device will not have the EPMP modules. Extending the RAM size is necessary for applications that require larger display buffers and work areas. It is recommended that the display buffers and work areas are not mapped into an area that overlaps the internal RAM and the external RAM. The external RAM can be interfaced using the EPMP module. For details, refer to the "PIC24F Family Reference Manual", Section 42. "Enhanced Parallel Master Port (EPMP)" (DS39730). TABLE 22-1: BUFFER MEMORY REQUIREMENTS vs. DISPLAY CONFIGURATION Display Buffer Memory Requirements (Bytes) 1 Bpp 16320 9600 4800 3200 2400 1024 2 Bpp 32640 19200 9600 6400 4800 2048 4 Bpp 65280 38400 19200 12800 9600 4096 8 Bpp 130560 76800 38400 25600 19200 8192 16 Bpp 261120 153600 76800 51200 38400 16384 Display Resolution 480x272 (WQVGA) 320x240 (QVGA) 240x160 (HQVGA) 160x160 160x120 (QQVGA) 128x64 Legend: Less than 24-Kbyte RAM variants (PIC24FJXXXDA106) Less than 96-Kbyte RAM variants (PIC24FJXXXDA2XX) External Memory with 96 Kbytes/24 Kbytes of RAM variants (PIC24FJXXXDAX10) DS39969B-page 324 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 23.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 17. "10-Bit A/D Converter" (DS39705). The information in this data sheet supersedes the information in the FRM. A block diagram of the A/D Converter is shown in Figure 23-1. To perform an A/D conversion: 1. Configure the A/D module: a) Configure the port pins as analog inputs and/or select band gap reference inputs (ANCFG registers). b) Select the voltage reference source to match the expected range on analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:5> and AD1CON3<12:8>). e) Select how the conversion results are presented in the buffer (AD1CON1<9:8>). f) Select the interrupt rate (AD1CON2<6:2>). g) Turn on the A/D module (AD1CON1<15>). Configure the A/D interrupt (if required): a) Clear the AD1IF bit. b) Select the A/D interrupt priority. The 10-bit A/D Converter has the following key features: * Successive Approximation (SAR) conversion * Conversion speeds of up to 500 ksps * 24 analog input pins (PIC24FJXXXDAX10 devices) and 16 analog input pins (PIC24FJXXXDAX06 devices) * External voltage reference input pins * Internal band gap reference inputs * Automatic Channel Scan mode * Selectable conversion trigger source * 32-word conversion result buffer * Selectable Buffer Fill modes * Four result alignment options * Operation during CPU Sleep and Idle modes On all PIC24FJ256DA210 family devices, the 10-bit A/D Converter has 24 analog input pins, designated AN0 through AN23. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins. 2. 2010 Microchip Technology Inc. DS39969B-page 325 PIC24FJ256DA210 FAMILY FIGURE 23-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD AVSS VREF+ VREFVINH AN0 AN1 AN2 VINH 10-Bit SAR Conversion Logic VINL S/H VRVR+ VR Select VR+ 16 VRComparator DAC MUX A Data Formatting VINL AD1BUF0: AD1BUF1F AD1CON1 AD1CON2 AD1CON3 MUX B VINH AD1CHS ANCFG AD1CSSL AD1CSSH AN23 VBG VBG/2 VBG/6 VCAP VINL Sample Control Input MUX Control Pin Config Control Control Logic Conversion Control DS39969B-page 326 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 23-1: R/W-0 ADON(1) bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 -- U-0 -- R/W-0 ASAM R-0, HSC SAMP AD1CON1: A/D CONTROL REGISTER 1 U-0 -- R/W-0 ADSIDL U-0 -- U-0 -- U-0 -- R/W-0 FORM1 R/W-0 FORM0 bit 8 R-0, HSC DONE bit 0 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as `0' ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' FORM<1:0>: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU event ends sampling and starts conversion 101 = Reserved 100 = Timer5 compare ends sampling and starts conversion 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Unimplemented: Read as `0' ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after the last conversion completes. The SAMP bit is auto-set. 0 = Sampling begins when the SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done The values of the ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module. bit 14 bit 13 bit 12-10 bit 9-8 bit 7-5 bit 4-3 bit 2 bit 1 bit 0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 327 PIC24FJ256DA210 FAMILY REGISTER 23-2: R/W-0 VCFG2 bit 15 R-0, HSC BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 r = Reserved bit W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SMPI4 R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM AD1CON2: A/D CONTROL REGISTER 2 R/W-0 VCFG0 r-0 r U-0 -- R/W-0 CSCNA U-0 -- U-0 -- bit 8 R/W-0 ALTS bit 0 R/W-0 VCFG1 VCFG<2:0>: Voltage Reference Configuration bits VCFG<2:0> 000 001 010 011 1xx VR+ AVDD External VREF+ pin AVDD External VREF+ pin AVDD VRAVSS AVSS External VREF- pin External VREF- pin AVSS bit 12 bit 11 bit 10 Reserved: Maintain as `0' Unimplemented: Read as `0' CSCNA: Scan Input Selections for the CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as `0' BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer, 10-1F, user should access data in 00-0F 0 = A/D is currently filling buffer, 00-0F, user should access data in 10-1F SMPI<4:0>: Sample/Convert Sequences Per Interrupt Selection bits 11111 = Interrupts at the completion of conversion for each 32nd sample/convert sequence 11110 = Interrupts at the completion of conversion for each 31st sample/convert sequence . . . 00001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 00000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer is configured as two 16-word buffers (ADC1BUFn<31:16> and ADC1BUFn<15:0>) 0 = Buffer is configured as one 32-word buffer (ADC1BUFn<31:0>) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for the first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses the MUX A input multiplexer settings bit 9-8 bit 7 bit 6-2 bit 1 bit 0 DS39969B-page 328 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 23-3: R/W-0 ADRC bit 15 R/W-0 ADCS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 r = Reserved bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ADCS6 R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1 r AD1CON3: A/D CONTROL REGISTER 3 r-0 r-0 r R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock is derived from the system clock Reserved: Maintain as `0' SAMC<4:0>: Auto-Sample Time bits 11111 = 31 TAD . . . 00001 = 1 TAD 00000 = 0 TAD (not recommended) ADCS<7:0>: A/D Conversion Clock Select bits 11111111 = 256 * TCY ****** 00000001 = 2 * TCY 00000000 = TCY bit 14-13 bit 12-8 bit 7-0 2010 Microchip Technology Inc. DS39969B-page 329 PIC24FJ256DA210 FAMILY REGISTER 23-4: R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 CH0SA4 (1) AD1CHS: A/D INPUT SELECT REGISTER U-0 -- U-0 -- R/W-0 CH0SB4(1) R/W-0 CH0SB3(1) R/W-0 CH0SB2(1) R/W-0 CH0SB1(1) R/W-0 CH0SB0(1) bit 8 R/W-0 CH0SA3 (1) R/W-0 CH0SA2 (1) R/W-0 CH0SA1 (1) R/W-0 CH0SA0(1) bit 0 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' CH0SB<4:0>: Channel 0 Positive Input Select for MUX B(1) Other = Not available; do not use 11111 = No channel used; all inputs are floating; used for CTMU 11011 = Channel 0 positive input is the band gap divided-by-six reference (VBG/6) 11010 = Channel 0 positive input is the core voltage (VCAP) 11001 = Channel 0 positive input is the band gap reference (VBG) 11000 = Channel 0 positive input is the band gap divided-by-two reference (VBG/2) 10111 = Channel 0 positive input is AN23(2) . . . 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as `0' CH0SA<4:0>: Channel 0 Positive Input Select for MUX(1) Other = Not available; do not use 11111 = No Channel used; all inputs are floating; used for CTMU 11011 = Channel 0 positive input is the band gap divided-by-six reference (VBG/6) 11010 = Channel 0 positive input is the core voltage (VCAP) 11001 = Channel 0 positive input is the band gap reference (VBG) 11000 = Channel 0 positive input is the band gap divided-by-two reference (VBG/2) 10111 = Channel 0 positive input is AN23(2) . . . 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 Combinations not shown here (11100 to 11110) are unimplemented; do not use. Channel 0 positive inputs, AN16 through AN23, are not available on 64-pin devices (PIC24FJXXXDAX06). bit 14-13 bit 12-8 bit 7 bit 6-5 bit 4-0 Note 1: 2: DS39969B-page 330 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 23-5: U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 VBG6EN R/W-0 VBG2EN ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 8 R/W-0 VBGEN bit 0 Unimplemented: Read as `0' VBG6EN: A/D Input VBG/6 Enable bit 1 = Band gap voltage divided-by-six reference (VBG/6) is enabled 0 = Band gap divided-by-six reference (VBG/6) is disabled VBG2EN: A/D Input VBG/2 Enable bit 1 = Band gap voltage divided-by-two reference (VBG/2) is enabled 0 = Band gap divided-by-two reference (VBG/2) is disabled VBGEN: A/D Input VBG Enable bit 1 = Band gap voltage reference (VBG) is enabled 0 = Band gap reference (VBG) is disabled bit 1 bit 0 REGISTER 23-6: R/W-0 CSSL15 bit 15 R/W-0 CSSL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) R/W-0 CSSL13 R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8 bit 8 R/W-0 CSSL14 R/W-0 CSSL6 R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W-0 CSSL1 R/W-0 CSSL0 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CSSL<15:0>: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel is selected for input scan 0 = Analog channel is omitted from input scan 2010 Microchip Technology Inc. DS39969B-page 331 PIC24FJ256DA210 FAMILY REGISTER 23-7: U-0 -- bit 15 R/W-0 CSSL23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown (1) AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH) U-0 -- U-0 -- U-0 -- R/W-0 CSSL27 R/W-0 CSSL26 R/W-0 CSSL25 R/W-0 CSSL24 bit 8 R/W-0 CSSL22 (1) R/W-0 CSSL21 (1) R/W-0 CSSL20 (1) R/W-0 CSSL19 (1) R/W-0 CSSL18 (1) R/W-0 CSSL17 (1) R/W-0 CSSL16(1) bit 0 Unimplemented: Read as `0' CSSL27: A/D Input Band Gap Scan Selection bit 1 = Band gap divided-by-six reference (VBG/6) is selected for input scan 0 = Analog channel is omitted from input scan CSSL26: A/D Input Band Gap Scan Selection bit 1 = Internal core voltage (VCAP) is selected for input scan 0 = Analog channel is omitted from input scan CSSL25: A/D Input Half Band Gap Scan Selection bit 1 = Band gap reference (VBG) is selected for input scan 0 = Analog channel is omitted from input scan CSSL24: A/D Input Band Gap Scan Selection bit 1 = Band gap divided-by-two reference (VBG/2) is selected for input scan 0 = Analog channel is omitted from input scan CSSL<23:16>: Analog Input Pin Scan Selection bits(1) 1 = Corresponding analog channel selected for input scan 0 = Analog channel is omitted from input scan Unimplemented in 64-pin devices, read as `0'. bit 10 bit 9 bit 8 bit 7-0 Note 1: EQUATION 23-1: A/D CONVERSION CLOCK PERIOD(1) ADCS = TAD -1 TCY TAD = TCY * (ADCS = 1) Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. DS39969B-page 332 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 23-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA ANx CPIN 6-11 pF (Typical) VT = 0.6V RIC 250 Sampling Switch RSS ILEAKAGE 500 nA CHOLD = DAC Capacitance = 4.4 pF (Typical) VSS RSS 5 k(Typical) VT = 0.6V Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from DAC) Note: CPIN value depends on the device package and is not tested. The effect of CPIN IS negligible if Rs 5 k. FIGURE 23-3: Output Code (Binary (Decimal)) A/D TRANSFER FUNCTION 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) 1023*(VR+ - VR-) 512*(VR+ - VR-) (VINH - VINL) VR+ - VRVR+ 1024 0 VR- 1024 Voltage Level VR- + VR- + 1024 2010 Microchip Technology Inc. DS39969B-page 333 VR- + PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 334 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 24.0 Note: TRIPLE COMPARATOR MODULE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated "PIC24F Family Reference Manual". The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals `1', the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module in shown in Figure 24-1. Diagrams of the possible individual comparator configurations are shown in Figure 24-2. Each comparator has its own control register, CMxCON (Register 24-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 24-2). The triple comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of five external analog inputs (CxINA, CxINB, CxINC, CxIND and VREF+) and a voltage reference input from one of the internal band gap references or the comparator voltage reference generator (VBG, VBG/2, VBG/6 and CVREF). FIGURE 24-1: CCH<1:0> TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL<1:0> Trigger/Interrupt Logic CEVT COE Input Select Logic CXINB CXINC CXIND VBG VBG/2 VBG/6 VREF+ CVREFM<1:0>(1) 00 01 10 11 00 01 10 11 CPOL VINVIN+ C1 COUT C1OUT Pin EVPOL<1:0> Trigger/Interrupt Logic CEVT COE CPOL VINVIN+ C2 COUT C2OUT Pin CXINA VREF+ CVREF CVREFP(1) 0 1 0 1 EVPOL<1:0> + CPOL C3 COUT C3OUT Pin Trigger/Interrupt Logic CEVT COE VINVIN+ CREF Note 1: Refer Register 25-1 for bit details. 2010 Microchip Technology Inc. DS39969B-page 335 PIC24FJ256DA210 FAMILY FIGURE 24-2: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0 Comparator Off CEN = 0, CREF = x, CCH<1:0> = xx VINVIN+ COE Cx Off (Read as `0') CxOUT Pin Comparator CxINB > CxINA Compare CEN = 1, CCH<1:0> = 00 VINVIN+ CVREFM<1:0> = xx COE Comparator CxINC > CxINA Compare CEN = 1, CCH<1:0> = 01 VINVIN+ CVREFM<1:0> = xx COE CXINB CXINA Cx CxOUT Pin CXINC CXINA Cx CxOUT Pin Comparator CxIND > CxINA Compare CEN = 1, CCH<1:0> = 10 VINVIN+ CVREFM<1:0> = xx COE Comparator VBG > CxINA Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 00 COE CXIND CXINA Cx CxOUT Pin VBG CXINA Cx CxOUT Pin Comparator VBG > CxINA Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 01 COE Comparator VBG > CxINA Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 10 COE VBG/2 CXINA Cx CxOUT Pin VBG/6 CXINA Cx CxOUT Pin Comparator CxIND > CxINA Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 11 COE VREF+ CXINA Cx CxOUT Pin DS39969B-page 336 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 24-3: CEN = 1, CCH<1:0> = 00 VINVIN+ INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0 Comparator CxINC > CVREF Compare CEN = 1, CCH<1:0> = 01 COE CXINC VINVIN+ CVREFM<1:0> = xx COE CVREFM<1:0> = xx Comparator CxINB > CVREF Compare CXINB CVREF Cx CxOUT Pin Cx CxOUT Pin CVREF Comparator CxIND > CVREF Compare CEN = 1, CCH<1:0> = 10 VINVIN+ CVREFM<1:0> = xx COE Comparator VBG > CVREF Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 00 COE CXIND CVREF VBG Cx CxOUT Pin Cx CxOUT Pin CVREF Comparator VBG > CVREF Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 01 COE Comparator VBG > CVREF Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 10 COE VBG/2 CVREF VBG/6 Cx CxOUT Pin Cx CxOUT Pin CVREF Comparator CxIND > CVREF Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 11 COE VREF+ CVREF Cx CxOUT Pin FIGURE 24-4: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 1 Comparator CxINC > CVREF Compare CEN = 1, CCH<1:0> = 01 VINVIN+ CVREFM<1:0> = xx COE CVREFM<1:0> = xx COE CXINC Comparator CxINB > CVREF Compare CEN = 1, CCH<1:0> = 00 VINVIN+ CXINB VREF+ Cx CxOUT Pin Cx CxOUT Pin VREF+ Comparator CxIND > CVREF Compare CEN = 1, CCH<1:> = 10 VINVIN+ CVREFM<1:0> = xx COE Comparator VBG > CVREF Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 00 COE CXIND VREF+ VBG Cx CxOUT Pin Cx CxOUT Pin VREF+ Comparator VBG > CVREF Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 01 COE Comparator VBG > CVREF Compare CEN = 1, CCH<1:0> = 11 VINVIN+ CVREFM<1:0> = 10 COE VBG/2 VREF+ VBG/6 Cx CxOUT Pin Cx CxOUT Pin VREF+ 2010 Microchip Technology Inc. DS39969B-page 337 PIC24FJ256DA210 FAMILY REGISTER 24-1: R/W-0 CEN bit 15 R/W-0 EVPOL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit `1' = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 EVPOL0 U-0 -- R/W-0 CREF U-0 -- U-0 -- R/W-0 CCH1 CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 CPOL U-0 -- U-0 -- U-0 -- R/W-0, HS CEVT R-0, HSC COUT bit 8 R/W-0 CCH0 bit 0 COE R/W-0 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted Unimplemented: Read as `0' CEVT: Comparator Event bit 1 = Comparator event that is defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINEVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled Unimplemented: Read as `0' bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7-6 bit 5 DS39969B-page 338 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 24-1: bit 4 CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CXINA pin Unimplemented: Read as `0' CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM<1:0> bits in the CVRCON register 10 = Inverting input of the comparator connects to the CXIND pin 01 = Inverting input of the comparator connects to the CXINC pin 00 = Inverting input of the comparator connects to the CXINB pin bit 3-2 bit 1-0 REGISTER 24-2: R/W-0 CMIDL bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15 CMSTAT: COMPARATOR MODULE STATUS REGISTER U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC C3EVT R-0, HSC C2EVT R-0, HSC C1EVT bit 8 U-0 -- U-0 -- U-0 -- U-0 -- R-0, HSC C3OUT R-0, HSC C2OUT R-0, HSC C1OUT bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode Unimplemented: Read as `0' C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON<9>). C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON<9>). C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). Unimplemented: Read as `0' C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON<8>). C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>). bit 14-11 bit 10 bit 9 bit 8 bit 7-3 bit 2 bit 1 bit 0 2010 Microchip Technology Inc. DS39969B-page 339 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 340 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 25.0 Note: COMPARATOR VOLTAGE REFERENCE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 19. "Comparator Module" (DS39710). The information in this data sheet supersedes the information in the FRM. 25.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 25-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 8R CVR<3:0> CVREN R R R 16-to-1 MUX R 16 Steps CVREF CVROE R R R CVREF Pin CVRR VREFCVRSS = 1 8R CVRSS = 0 AVSS 2010 Microchip Technology Inc. DS39969B-page 341 PIC24FJ256DA210 FAMILY REGISTER 25-1: U-0 -- bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CVREFP R/W-0 CVREFM1 R/W-0 CVREFM0 bit 8 R/W-0 CVR0 bit 0 Unimplemented: Read as `0' CVREFP: Voltage Reference Select bit (valid only when CREF is `1') 1 = VREF+ is used as a reference voltage to the comparators 0 = The CVR (4-bit DAC) within this module provides the the reference voltage to the comparators CVREFM<1:0>: Band Gap Reference Source Select bits (valid only when CCH<1:0> = 11) 00 = Band gap voltage is provided as an input to the comparators 01 = Band gap voltage divided-by-two is provided as an input to the comparators 10 = Band gap voltage divided-by-six is provided as an input to the comparators 11 = VREF+ pin is provided as an input the comparators CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ - VREF0 = Comparator reference source CVRSRC = AVDD - AVSS CVR<3:0>: Comparator VREF Value Selection 0 CVR<3:0> 15 bits When CVRR = 1: CVREF = (CVR<3:0>/ 24) (CVRSRC) When CVRR = 0: CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC) bit 9-8 bit 7 bit 6 bit 5 bit 4 bit 3-0 DS39969B-page 342 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 26.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated "PIC24F Family Reference Manual", Section 11. "Charge Time Measurement Unit (CTMU)" (DS39724). The information in this data sheet supersedes the information in the FRM. source polarity selection, and edge sequencing. The CTMUICON register controls the selection and trim of the current source. 26.1 Measuring Capacitance The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: * * * * * * Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module's precision current source to calculate capacitance according to the relationship: dV C = I -----dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output's pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 26-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the "PIC24F Family Reference Manual". Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers: CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge FIGURE 26-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 EDG2 Output Pulse A/D Converter ANx ANY Current Source CAPP RPR 2010 Microchip Technology Inc. DS39969B-page 343 PIC24FJ256DA210 FAMILY 26.2 Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module's internal capacitor (CAD) and a precision resistor for current calibration. Figure 26-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the "PIC24F Family Reference Manual". When the module is configured for pulse generation delay by setting the TGEN (CTMUCON<12>) bit, the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Figure 26-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the "PIC24F Family Reference Manual". 26.3 Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device's system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. FIGURE 26-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT TIME PIC24F Device CTMU CTEDG1 CTEDG2 EDG1 EDG2 Output Pulse A/D Converter CAD RPR Current Source ANx FIGURE 26-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB C2 CDELAY CVREF DS39969B-page 344 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 26-1: R/W-0 CTMUEN bit 15 R/W-0 EDG2POL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 EDG2SEL1 R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0, HSC EDG2STAT CTMUCON: CTMU CONTROL REGISTER U-0 -- R/W-0 CTMUSIDL R/W-0 TGEN(1) R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN R/W-0 CTTRIG bit 8 R/W-0, HSC EDG1STAT bit 0 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as `0' CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response EDG2SEL<1:0>: Edge 2 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 14 bit 13 bit 12 bit 10 bit 10 bit 9 bit 8 bit 7 bit 6-5 bit 4 Note 1: 2010 Microchip Technology Inc. DS39969B-page 345 PIC24FJ256DA210 FAMILY REGISTER 26-1: bit 3-2 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 "Peripheral Pin Select (PPS)" for more information. bit 1 bit 0 Note 1: REGISTER 26-2: R/W-0 ITRIM5 bit 15 U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 8 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 R/W-0 ITRIM4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current IRNG<1:0>: Current Source Range Select bits 11 = 100 Base Current 10 = 10 Base Current 01 = Base current level (0.55 A nominal) 00 = Current source is disabled Unimplemented: Read as `0' bit 9-8 bit 7-0 DS39969B-page 346 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 27.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the "PIC24F Family Reference Manual". The information in this data sheet supersedes the information in the FRMs. * Section 9. "Watchdog Timer (WDT)" (DS39697) * Section 32. "High-Level Device Integration" (DS39719) * Section 33. "Programming and Diagnostics" (DS39716) 27.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ256DA210 FAMILY DEVICES In PIC24FJ256DA210 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 27-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device Resets. PIC24FJ256DA210 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * * * Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial ProgrammingTM In-Circuit Emulation When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The upper byte of all Flash Configuration Words in program memory should always be `0000 0000'. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `0's to these locations has no effect on device operation. Note: Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. 27.1 Configuration Bits The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 27-1 through Register 27-6. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 27-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ256DA210 FAMILY DEVICES Configuration Word Addresses 1 157FEh 2ABFEh 2 157FCh 2ABFCh 3 157FAh 2ABFAh 4 157F8h 2ABF8h Device PIC24FJ128DAXXX PIC24FJ256DAXXX 2010 Microchip Technology Inc. DS39969B-page 347 PIC24FJ256DA210 FAMILY REGISTER 27-1: U-0 -- bit 23 r-x reserved bit 15 R/PO-1 FWDTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 bit 14 r = Reserved bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/PO-1 WINDIS R/PO-1 ALTVREF(1) R/PO-1 FWPSA R/PO-1 WDTPS3 R/PO-1 WDTPS2 R/PO-1 WDTPS1 R/PO-1 JTAGEN R/PO-1 GCP R/PO-1 GWRP R/PO-1 DEBUG r-1 reserved R/PO-1 ICS1 CW1: FLASH CONFIGURATION WORD 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 R/PO-1 ICS0 bit 8 R/PO-1 WDTPS0 bit 0 Unimplemented: Read as `1' Reserved: The value is unknown; program as `0' JTAGEN: JTAG Port Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are not allowed DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode Reserved: Always maintain as `1' ICS<1:0>: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled; FWDTEN must be `1' ALTVREF: Alternate VREF Pin Selection bit(1) 1 = VREF is on a default pin (VREF+ on RA10 and VREF- on RA9) 0 = VREF is on an alternate pin (VREF+ on RB0 and VREF- on RB1) Unimplemented in 64-pin devices, maintain at `1' (VREF+ on RB0 and VREF- on RB1). bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 Note 1: DS39969B-page 348 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 27-1: bit 4 CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Unimplemented in 64-pin devices, maintain at `1' (VREF+ on RB0 and VREF- on RB1). bit 3-0 Note 1: 2010 Microchip Technology Inc. DS39969B-page 349 PIC24FJ256DA210 FAMILY REGISTER 27-2: U-0 -- bit 23 R/PO-1 IESO bit 15 R/PO-1 FCKSM1 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 r = Reserved bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY r-1 reserved r-1 reserved R/PO-1 POSCMD1 R/PO-1 PLLDIV2 R/PO-1 PLLDIV1 R/PO-1 PLLDIV0 R/PO-1 PLL96MHZ R/PO-1 FNOSC2 R/PO-1 FNOSC1 CW2: FLASH CONFIGURATION WORD 2 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 R/PO-1 FNOSC0 bit 8 R/PO-1 POSCMD0 bit 0 Unimplemented: Read as `1' IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) is enabled 0 = IESO mode (Two-Speed Start-up) is disabled PLLDIV<2:0>: 96 MHz PLL Prescaler Select bits 111 = Oscillator input is divided by 12 (48 MHz input) 110 = Oscillator input is divided by 8 (32 MHz input) 101 = Oscillator input is divided by 6 (24 MHz input) 100 = Oscillator input is divided by 5 (20 MHz input) 011 = Oscillator input is divided by 4 (16 MHz input) 010 = Oscillator input is divided by 3 (12 MHz input) 001 = Oscillator input is divided by 2 (8 MHz input) 000 = Oscillator input is used directly (4 MHz input) PLL96MHZ: 96 MHz PLL Start-Up Enable bit 1 = 96 MHz PLL is enabled automatically on start-up 0 = 96 MHz PLL is software controlled (can be enabled by setting the PLLEN bit in CLKDIV<5>) FNOSC<2:0>: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD<1:0> = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD<1:0> = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 DS39969B-page 350 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 27-2: bit 4 CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed Reserved: Always maintain as `1' POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected bit 3-2 bit 1-0 REGISTER 27-3: U-0 -- bit 23 R/PO-1 WPEND bit 15 R/PO-1 WPFP7 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 CW3: FLASH CONFIGURATION WORD 3 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 R/PO-1 WPCFG R/PO-1 WPDIS R/PO-1 ALTPMP(1) R/PO-1 WUTSEL1 R/PO-1 WUTSEL0 R/PO-1 SOSCSEL1 R/PO-1 SOSCSEL0 bit 8 R/PO-1 WPFP6 R/PO-1 WPFP5 R/PO-1 WPFP4 R/PO-1 WPFP3 R/PO-1 WPFP2 R/PO-1 WPFP1 R/PO-1 WPFP0 bit 0 PO = Program-Once bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `1' WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment upper boundary is at the last page of program memory; the lower boundary is the code page specified by WPFP<7:0> 0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper boundary is the code page specified by WPFP<7:0> WPCFG: Configuration Word Code Page Write Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected(3) 0 = Last page and Flash Configuration Words are write-protected, provided WPDIS = `0' WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection is disabled 0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and WPFPx Configuration bits ALTPMP: Alternate EPMP Pin Mapping bit(1) 1 = EPMP pins are in default location mode 0 = EPMP pins are in alternate location mode Unimplemented in 64-pin devices, maintain at `1'. Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-1. Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word's page, the Configuration Word's page is protected. bit 14 bit 13 bit 12 Note 1: 2: 3: 2010 Microchip Technology Inc. DS39969B-page 351 PIC24FJ256DA210 FAMILY REGISTER 27-3: bit 11-10 CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) WUTSEL<1:0>: Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator start-up time is used 01 = Fast regulator start-up time is used x0 = Reserved; do not use SOSCSEL<1:0>: SOSC Selection Configuration bits 11 = Secondary oscillator is in Default (high drive strength) Oscillator mode 10 = Reserved; do not use 01 = Secondary oscillator is in Low-Power (low drive strength) Oscillator mode 00 = External clock (SCLKI) or Digital I/O mode(2) WPFP<7:0>: Write Protected Code Segment Boundary Page bits Designates the 512 instruction words page boundary of the protected code segment. If WPEND = 1: Specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device. If WPEND = 0: Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary. Unimplemented in 64-pin devices, maintain at `1'. Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-1. Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word's page, the Configuration Word's page is protected. bit 9-8 bit 7-0 Note 1: 2: 3: REGISTER 27-4: U-0 -- bit 23 r-1 reserved bit 15 r-1 reserved bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15-0 CW4: FLASH CONFIGURATION WORD 4 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 r-1 r-1 reserved r-1 reserved r-1 reserved r-1 reserved r-1 reserved r-1 reserved bit 8 r-1 r-1 reserved r-1 reserved r-1 reserved r-1 reserved r-1 reserved r-1 reserved bit 0 r = Reserved bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown reserved reserved Unimplemented: Read as `0' Reserved: Always maintain as `1' DS39969B-page 352 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 27-5: U-0 -- bit 23 R FAMID7 bit 15 R DEV7 bit 7 Legend: R = Readable bit bit 23-16 bit 15-8 bit 7-0 Unimplemented: Read as `1' FAMID<7:0>: Device Family Identifier bits 01000001 = PIC24FJ256DA210 family DEV<7:0>: Individual Device Identifier bits 00001000 = PIC24FJ128DA206 00001001 = PIC24FJ128DA106 00001010 = PIC24FJ128DA210 00001011 = PIC24FJ128DA110 00001100 = PIC24FJ256DA206 00001101 = PIC24FJ256DA106 00001110 = PIC24FJ256DA210 00001111 = PIC24FJ256DA110 U = Unimplemented bit R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 R FAMID1 R FAMID0 bit 8 DEVID: DEVICE ID REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 2010 Microchip Technology Inc. DS39969B-page 353 PIC24FJ256DA210 FAMILY REGISTER 27-6: U-0 -- bit 23 U-0 -- bit 15 U-0 -- bit 7 Legend: R = Readable bit bit 23-4 bit 3-0 Unimplemented: Read as `0' REV<3:0>: Device revision identifier bits U = Unimplemented bit U-0 -- U-0 -- U-0 -- R REV3 R REV2 R REV1 R REV0 bit 0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- DEVREV: DEVICE REVISION REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 16 U-0 -- bit 8 27.2 On-Chip Voltage Regulator All PIC24FJ256DA210 family devices power their core digital logic at a nominal 1.8V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256DA210 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR capacitor (such as ceramic) must be connected to the VCAP pin (Figure 27-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor (CEFC) is provided in Section 30.1 "DC Characteristics". Low-Voltage Detect Interrupt Flag, LVDIF (IFS4<8>). This can be used to generate an interrupt to trigger an orderly shutdown. FIGURE 27-1: CONNECTIONS FOR THE ON-CHIP REGULATOR 3.3V(1) PIC24FJXXXDA1/DA2 VDD ENVREG VCAP Regulator Enabled (ENVREG tied to VDD): CEFC (10 F typ) Note 1: VSS 27.2.1 VOLTAGE REGULATOR LOW-VOLTAGE DETECTION 27.2.2 This is a typical operating voltage. Refer to Section 30.1 "DC Characteristics" for the full operating ranges of VDD. When the on-chip regulator is enabled, it provides a constant voltage of 1.8V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.1V, all the way up to the device's VDDMAX. It does not have the capability to boost VDD levels. In order to prevent "brown-out" conditions when the voltage drops too low for the regulator, the Brown-out Reset occurs. Then the regulator output follows VDD with a typical voltage drop of 300 mV. To provide information about when the regulator voltage starts reducing, the on-chip regulator includes a simple Low-Voltage Detect circuit, which sets the ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 10 s for it to generate output. During this time, designated as TVREG, code execution is disabled. TVREG is applied every time the device resumes operation after any power-down, including Sleep mode. TVREG is determined by the status of the VREGS bit (RCON<8>) and the WUTSEL Configuration bits (CW3<11:10>). Refer to Section 30.0 "Electrical Characteristics" for more information on TVREG. DS39969B-page 354 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 27.2.3 ON-CHIP REGULATOR AND BOR 27.3 Watchdog Timer (WDT) When the on-chip regulator is enabled, PIC24FJ256DA210 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the output level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR (RCON<1>) flag bit. The brown-out voltage specifications are provided in Section 7. "Reset" (DS39712) in the "PIC24F Family Reference Manual". Note: For more information, see Section 30.0 "Electrical Characteristics". The information in this data sheet supersedes the information in the FRM. For PIC24FJ256DA210 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT Time-out period (TWDT) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS<3:0> Configuration bits (CW1<3:0>), which allows the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler time-out periods, ranging from 1 ms to 131 seconds, can be achieved. The WDT, prescaler and postscaler are reset: * On any device Reset * On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) * When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) * When the device exits Sleep or Idle mode to resume normal operation * By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE (RCON<3:2>) bits will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. 27.2.4 VOLTAGE REGULATOR STANDBY MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator can be made to enter Standby mode on its own whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON<8>). Clearing the VREGS bit enables the Standby mode. When waking up from Standby mode, the regulator needs to wait for TVREG to expire before wake-up. The regulator wake-up time required for Standby mode is controlled by the WUTSEL<1:0> (CW3<11:10>) Configuration bits. The regulator wake-up time is lower when WUTSEL<1:0> = 01, and higher when WUTSEL<1:0> = 11. Refer to the TVREG specification in Table 30-10 for regulator wake-up time. When the regulator's Standby mode is turned off (VREGS = 1), the device wakes up without waiting for TVREG. However, with the VREGS bit set, the power consumption while in Sleep mode will be approximately 40 A higher than what it would be if the regulator was allowed to enter Standby mode. 2010 Microchip Technology Inc. DS39969B-page 355 PIC24FJ256DA210 FAMILY 27.3.1 WINDOWED OPERATION 27.3.2 CONTROL REGISTER The Watchdog Timer has an optional Fixed-Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1<6>) to `0'. The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN Control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. FIGURE 27-2: SWDTEN FWDTEN WDT BLOCK DIAGRAM LPRC Control FWPSA Prescaler (5-bit/7-bit) 31 kHz 1 ms/4 ms WDT Counter WDTPS<3:0> Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake from Sleep LPRC Input All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS39969B-page 356 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 27.4 Program Verification and Code Protection The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected, by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. A separate bit, WPCFG, is used to protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page in addition to the pages selected by the WPEND and WPFP<7:0> bits setting. This is useful in circumstances where write protection is needed for both the code segment in the bottom of the memory and the Flash Configuration Words. The various options for segment code protection are shown in Table 27-2. PIC24FJ256DA210 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 27.4.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ256DA210 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to `0', internal write and erase operations to program memory are blocked. 27.4.2 CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of write and erase-protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in the PIC24FJ256DA210 family devices can be located by the user anywhere in the program space and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. It does not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half. 2010 Microchip Technology Inc. DS39969B-page 357 PIC24FJ256DA210 FAMILY 27.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers - shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code segment protection setting. TABLE 27-2: WPDIS 1 0 CODE SEGMENT PROTECTION CONFIGURATION OPTIONS WPCFG x x Write/Erase Protection of Code Segment No additional protection is enabled; all program memory protection is configured by GCP and GWRP. Addresses from the first address of the code page are defined by WPFP<7:0> through the end of implemented program memory (inclusive), write/erase protected, including Flash Configuration Words. Address 000000h through the last address of the code page is defined by WPFP<7:0> (inclusive), write/erase protected. Address 000000h through the last address of code page is defined by WPFP<7:0> (inclusive), write/erase protected and the last page, including Flash Configuration Words are write/erase protected. Segment Configuration Bits WPEND X 1 0 0 0 0 1 0 27.5 JTAG Interface 27.7 In-Circuit Debugger PIC24FJ256DA210 family devices implement a JTAG interface, which supports boundary scan device testing. 27.6 In-Circuit Serial ProgrammingTM PIC24FJ256DA210 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power (VDD), ground (VSS) and MCLR. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. When MPLAB(R) ICD 3 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. DS39969B-page 358 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 28.0 DEVELOPMENT SUPPORT 28.1 The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2010 Microchip Technology Inc. DS39969B-page 359 PIC24FJ256DA210 FAMILY 28.2 MPLAB C Compilers for Various Device Families 28.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families 28.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS39969B-page 360 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 28.7 MPLAB SIM Software Simulator 28.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easy-to-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 28.8 MPLAB REAL ICE In-Circuit Emulator System 28.10 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2010 Microchip Technology Inc. DS39969B-page 361 PIC24FJ256DA210 FAMILY 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 28.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39969B-page 362 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 29.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The literal instructions that involve data movement may use some of the following operands: * A literal value to be loaded into a W register or file register (specified by the value of `k') * The W register or file register where the literal value is to be loaded (specified by `Wb' or `f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand which is a register `Wb' without any address modifier * The second source operand which is a literal value * The destination of the result (only if not the same as the first source operand), which is typically a register `Wd' with or without an address modifier The control instructions may use some of the following operands: * A program memory address * The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. The PIC24F instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Word or byte-oriented operations Bit-oriented operations Literal operations Control operations Table 29-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 29-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand which is typically a register `Wb' without any address modifier * The second source operand which is typically a register `Ws' with or without an address modifier * The destination of the result which is typically a register `Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value `f' * The destination, which could either be the file register `f' or the W0 register, which is denoted as `WREG' Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple * The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f') * The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb') 2010 Microchip Technology Inc. DS39969B-page 363 PIC24FJ256DA210 FAMILY TABLE 29-1: Field #text (text) [text] {} SYMBOLS USED IN OPCODE DESCRIPTIONS Description DS39969B-page 364 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSET BSET BSW BSW.C BSW.Z BTG BTG BTG BTSC BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 INSTRUCTION SET OVERVIEW Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws 1 None (2 or 3) 1 None (2 or 3) 2010 Microchip Technology Inc. DS39969B-page 365 PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CALL CALL CLR CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CP0 CP0 CPB CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW.B DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C DS39969B-page 366 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic GOTO GOTO GOTO INC INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP NOP NOPR POP POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None 2010 Microchip Technology Inc. DS39969B-page 367 PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic PWRSAV RCALL PWRSAV RCALL RCALL REPEAT REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP SWAP.b SWAP TBLRDH TBLRDH f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd #lit10,Wn INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f - WREG WREG = f - WREG Wn = Wn - lit10 Wd = Wb - Ws Wd = Wb - lit5 f = f - WREG - (C) WREG = f - WREG - (C) Wn = Wn - lit10 - (C) Wd = Wb - Ws - (C) Wd = Wb - lit5 - (C) f = WREG - f WREG = WREG - f Wd = Ws - Wb Wd = lit5 - Wb f = WREG - f - (C) WREG = WREG - f - (C) Wd = Ws - Wb - (C) Wd = lit5 - Wb - (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog<23:16> to Wd<7:0> # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None DS39969B-page 368 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Description Read Prog<15:0> to Wd Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N 2010 Microchip Technology Inc. DS39969B-page 369 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 370 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256DA210 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256DA210 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +100C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD < 3.0V............................................ -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD > 3.0V..................................................... -0.3V to (+5.5V) Voltage on VBUS pin with respect to VSS, independent of VDD or VUSB ................................................. -0.3V to (+5.5V) Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 30-1). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2010 Microchip Technology Inc. DS39969B-page 371 PIC24FJ256DA210 FAMILY 30.1 DC Characteristics PIC24FJ256DA210 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) FIGURE 30-1: 3.6V PIC24FJXXXDA1 Voltage (VDD) 2.2V VBOR 3.6V 2.2V VBOR Frequency Note: VCAP (nominal On-Chip Regulator output voltage) = 1.8V. 32 MHz TABLE 30-1: THERMAL OPERATING CONDITIONS Rating Symbol TJ TA PD PDMAX Min -40 -40 Typ -- -- PINT + PI/O (TJMAX - TA)/JA Max +125 +85 Unit C C W W PIC24FJ256DA210 family: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation (with ENVREG = 1): Internal Chip Power Dissipation: PINT = VDD x (IDD - IOH) I/O Pin Power Dissipation: PI/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 30-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol JA JA JA JA Typ 69.4 76.6 28.0 40.2 Max -- -- -- -- Unit C/W C/W C/W C/W Note (Note 1) (Note 1) (Note 1) (Note 1) Package Thermal Resistance, 12x12x1 mm TQFP Package Thermal Resistance, 10x10x1 mm TQFP Package Thermal Resistance, 9x9x0.9 mm QFN Package Thermal Resistance, 10x10x1.1 mm BGA Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS39969B-page 372 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 Supply Voltage VDD VCAP DC12 DC16 VDR VPOR (2) Characteristic VBOR -- RAM Data Retention Voltage(1) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal Brown-out Reset Voltage on VDD Transition, High-to-Low LVD Trip Voltage 1.5 Vss -- 1.8V -- -- 3.6 -- -- -- V V V V Regulator enabled Regulator enabled DC17 SVDD 0.05 -- -- V/ms 0-3.3V in 66 ms 0-2.5V in 50 ms Regulator enabled VBOR 2.0 2.10 2.2 V VLVD Note 1: 2: -- VBOR + 0.10 -- V This is the limit to which the RAM data can be retained, while the on-chip regulator output voltage starts following the VDD. This is the on-chip regulator output voltage specification. 2010 Microchip Technology Inc. DS39969B-page 373 PIC24FJ256DA210 FAMILY TABLE 30-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC20D DC20E DC20F DC23D DC23E DC23F DC24D DC24E DC24F DC31D DC31E DC31F Note 1: 2: Typical(1) Operating Current (IDD)(2) 0.8 0.8 0.8 3.0 3.0 3.0 12.0 12.0 12.0 55 55 135 1.3 1.3 1.3 4.8 4.8 4.8 18 18 18 95 95 225 mA mA mA mA mA mA mA mA mA A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.3V(3) LPRC (31 kHz) 3.3V(3) 16 MIPS 3.3V(3) 4 MIPS 3.3V(3) 1 MIPS 3: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. DS39969B-page 374 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC40D DC40E DC40F DC43D DC43E DC43F DC47D DC47E DC47F DC50D DC50E DC50F DC51D DC51E DC51F Note 1: 2: Typical(1) Idle Current (IIDLE)(2) 170 170 220 0.6 0.6 0.7 2.3 2.3 2.4 0.8 0.8 1.0 40.0 40.0 120.0 320 320 380 1.2 1.2 1.2 4.8 4.8 4.8 1.8 1.8 1.8 85 85 210 A A A mA mA mA mA mA mA mA mA mA A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C 3.3V (3) 3.3V(3) 1 MIPS 3.3V(3) 4 MIPS 3.3V(3) 16 MIPS FRC (4 MIPS) 3.3V(3) LPRC (31 kHz) 3: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off; OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. 2010 Microchip Technology Inc. DS39969B-page 375 PIC24FJ256DA210 FAMILY TABLE 30-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC60D DC60E DC60H DC60F DC61D DC61E DC61H DC61F DC62D DC62E DC62H DC62F DC63D DC63E DC63H DC63F Note 1: 2: Typical(1) Power-Down Current (IPD)(2) 20.0 20.0 55.0 95.0 1.0 1.0 1.0 2.5 1.5 1.5 1.5 8.0 4.0 4.0 6.5 12.0 45 45 105 185 3.5 3.5 3.5 6.5 6 6 6 18 18 18 18 25 A A A A A A A A A A A A A A A A -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C -40C +25C +60C +85C 3.3V(3) 3.3V(3) Low drive strength, 32 kHz crystal with RTCC or Timer1: ISOSC; SOSCSEL<1:0> = 01(4) 3.3V(3) 31 kHz LPRC oscillator with RTCC, WDT or Timer1:ILPRC(4) 3.3V(3) Base power-down current(4) 32 kHz crystal with RTCC or Timer1: ISOSC; SOSCSEL<1:0> = 11(4) 3: 4: Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with the device in Sleep mode (all peripherals and clocks are shut down). All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39969B-page 376 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbo No. l VIL DI10 DI11 DI15 DI16 DI17 DI18 DI19 VIH DI20 Characteristic Input Low Voltage(3) I/O Pins with ST Buffer I/O Pins with TTL Buffer MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I2CTM Buffer: I/O Pins with SMBus Buffer: Input High Voltage(3) I/O Pins with ST Buffer: with Analog Functions, Digital Only I/O Pins with TTL Buffer: with Analog Functions, Digital Only MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I2CTM Buffer: with Analog Functions, Digital Only I/O Pins with SMBus Buffer: with Analog Functions, Digital Only ICNPU ICNPD IIL DI50 DI51 DI55 DI56 Note 1: 2: 3: CNxx Pull-up Current CNxx Pull-down Current Input Leakage Current(2) I/O Ports Analog Input Pins MCLR OSCI/CLKI -- -- -- -- -- -- -- -- +1 +1 +1 +1 A A A A VSS VPIN VDD, pin at high-impedance VSS VPIN VDD, pin at high-impedance VSS VPIN VDD VSS VPIN VDD, EC, XT and HS modes 0.8 VDD 0.8 VDD 0.25 VDD + 0.8 0.25 VDD + 0.8 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 2.1 150 15 350 70 -- -- -- -- -- -- -- -- -- VDD 5.5 VDD 5.5 VDD VDD VDD VDD 5.5 VDD 5.5 550 150 V V V V V V V V V 2.5V VPIN VDD V V A A VDD = 3.3V, VPIN = VSS VDD = 3.3V, VPIN = VDD VSS VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- -- 0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 V V V V V V V SMBus enabled DI21 DI25 DI26 DI27 DI28 DI29 DI30 DI30A Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Negative current is defined as current sourced by the pin. Refer to Table 1-1 for I/O pins buffer types. 2010 Microchip Technology Inc. DS39969B-page 377 PIC24FJ256DA210 FAMILY TABLE 30-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. VOL DO10 DO16 VOH DO20 Characteristic Output Low Voltage I/O Ports OSCO/CLKO Output High Voltage I/O Ports 3.0 2.4 1.65 1.4 DO26 Note 1: OSCO/CLKO 2.4 1.4 -- -- -- -- -- -- -- -- -- -- -- -- V V V V V V IOH = -3.0 mA, VDD = 3.6V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.2V IOH = -3.0 mA, VDD = 2.2V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.2V -- -- -- -- -- -- -- -- 0.4 0.4 0.4 0.4 V V V V IOL = 6.6 mA, VDD = 3.6V IOL = 5.0 mA, VDD = 2.2V IOL = 6.6 mA, VDD = 3.6V IOL = 5.0 mA, VDD = 2.2V Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 30-9: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. D130 D131 D132B D133A TIW EP VPR Characteristic Program Flash Memory Cell Endurance VDD for Read VDD for Self-Timed Write Self-Timed Word Write Cycle Time Self-Timed Row Write Cycle Time D133B D134 D135 Note 1: TIE TRETD IDDP Self-Timed Page Erase Time Characteristic Retention Supply Current during Programming 10000 VMIN VMIN -- -- 20 20 -- -- -- -- 20 1.5 -- -- 16 -- 3.6 3.6 -- -- 40 -- -- E/W V V s ms ms Year mA -40C to +85C VMIN = Minimum operating voltage VMIN = Minimum operating voltage If no other specifications are violated Data in "Typ" column is at 3.3V, 25C unless otherwise stated. DS39969B-page 378 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40C < TA < +85C (unless otherwise stated) Param Symbol No. VRGOUT VBG CEFC Characteristics Regulator Output Voltage Internal Band Gap Reference External Filter Capacitor Value Min -- -- 4.7 Typ 1.8 1.2 10 Max Units -- -- -- V V F Series resistance < 3 Ohm recommended; < 5 Ohm required. VREGS = 1, VREGS = 0 with WUTSEL<1:0> = 01 or any POR or BOR Sleep wake-up with VREGS = 0 and WUTSEL<1:0> = 11 Comments TVREG -- 10 -- s -- TBG Band Gap Reference Start-up Time -- 190 1 -- -- s ms 30.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ256DA210 family AC characteristics and timing parameters. TABLE 30-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range as described in Section 30.1 "DC Characteristics". FIGURE 30-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 - for OSCO Load Condition 1 - for all pins except OSCO VDD/2 RL Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output 2010 Microchip Technology Inc. DS39969B-page 379 PIC24FJ256DA210 FAMILY TABLE 30-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSCO Characteristic OSCO/CLKO Pin Min -- Typ(1) -- Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSCI EC mode In I2CTM mode DO56 DO58 Note 1: CIO CB All I/O Pins and OSCO SCLx, SDAx -- -- -- -- 50 400 pF pF Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 30-3: Q4 EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS25 OS30 OS30 OS31 OS31 CLKO OS40 OS41 DS39969B-page 380 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. OS10 FOSC Characteristic External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min DC 4 3.5 4 10 10 31 -- 62.5 0.45 x TOSC -- -- -- Typ(1) -- -- -- -- -- -- -- -- -- -- -- 6 6 Max 32 48 10 8 32 32 33 -- DC -- 20 10 10 Units MHz MHz MHz MHz MHz MHz kHz -- ns ns ns ns ns EC EC EC ECPLL XT XTPLL HS HSPLL SOSC See parameter OS10 for FOSC value Conditions OS20 TOSC OS25 TCY OS30 TosL, TosH OS31 TosR, TosF OS40 TckR OS41 TckF Note 1: 2: TOSC = 1/FOSC Instruction Cycle Time(2) External Clock in (OSCI) High or Low Time External Clock in (OSCI) Rise or Fall Time CLKO Rise Time(3) CLKO Fall Time(3) 3: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). TABLE 30-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.2V TO 3.6V) AC CHARACTERISTICS Param Symbol No. OS50 FPLLI Characteristic(1) PLL Input Frequency Range(2) PLL Output Frequency Range PLL Start-up Time (Lock Time) CLKO Stability (Jitter) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min 4 4 4 OS51 OS52 OS53 FSYS TLOCK DCLK 95.76 -- -0.25 -- -- -- Typ(2) -- Max 48 32 8 96.24 200 0.25 Units MHz MHz MHz MHz s % Conditions ECPLL mode HSPLL mode XTPLL mode Note 1: 2: These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2010 Microchip Technology Inc. DS39969B-page 381 PIC24FJ256DA210 FAMILY TABLE 30-15: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F20 F21 Note 1: 2: Characteristic FRC Accuracy @ 8 MHz(1,2) LPRC @ 31 kHz Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min -1 -20 Typ 0.15 -- Max 1 20 Units % % Conditions -40C TA +85C -40C TA +85C 2.2V VDD 3.6V VCAP (on-chip regulator output voltage) = 1.8V Frequency calibrated at 25C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum. TABLE 30-16: RC OSCILLATOR START-UP TIME AC CHARACTERISTICS Param No. TFRC TLPRC Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min -- -- Typ 15 50 Max -- -- Units s s Conditions TABLE 30-17: RESET AND BROWN-OUT RESET REQUIREMENTS AC CHARACTERISTICS Param Symbol No. SY10 SY12 SY13 SY25 TMCL TPOR TIOZ TBOR TRST Characteristic MCLR Pulse width (Low) Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Internal State Reset Time Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min 2 -- -- 1 -- Typ -- 2 -- -- 50 Max -- -- 100 -- -- Units s s ns s s VDD VBOR Conditions DS39969B-page 382 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 30-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value DO31 DO32 Note: Refer to Figure 30-2 for load conditions. Old Value TABLE 30-18: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. DO31 DO32 DI35 DI40 Note 1: TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time (input) CNx High or Low Time (input) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min -- -- 20 2 Typ(1) 10 10 -- -- Max 25 25 -- -- Units ns ns ns TCY Conditions Data in "Typ" column is at 3.3V, 25C unless otherwise stated. 2010 Microchip Technology Inc. DS39969B-page 383 PIC24FJ256DA210 FAMILY TABLE 30-19: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. AD01 Symbol Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min. Typ Max. Units Conditions Device Supply AVDD Module VDD Supply Greater of VDD - 0.3 or 2.2 VSS - 0.3 AVSS + 1.7 AVSS AVSS - 0.3 -- Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD - 1.7 AVDD + 0.3 V AD02 AD05 AD06 AD07 AVSS VREFH VREFL VREF Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage -- -- -- -- V V V V Reference Inputs Analog Input AD10 AD11 AD12 AD13 VINH-VINL Full-Scale Input Span VIN VINL Absolute Input Voltage Absolute VINL Input Voltage Leakage Current VREFL AVSS - 0.3 AVSS - 0.3 -- 1.0 -- -- VREFH AVDD + 0.3 AVDD/2 610 V V V nA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k 10-bit (Note 2) AD17 RIN Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) -- -- 2.5K ADC Accuracy AD20B Nr AD21B INL AD22B DNL AD23B GERR AD24B EOFF AD25B Note 1: 2: -- -- -- -- -- -- 10 1 0.5 1 1 -- -- <2 <1 3 2 -- bits LSb LSb LSb LSb -- VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Guaranteed The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. Measurements taken with external VREF+ and VREF- used as the ADC voltage reference. DS39969B-page 384 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-20: ADC CONVERSION TIMING REQUIREMENTS(1) AC CHARACTERISTICS Param No. AD50 AD51 Symbol Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C Min. Typ Max. Units Conditions Clock Parameters TAD tRC ADC Clock Period ADC Internal RC Oscillator Period Conversion Time Throughput Rate Sample Time Sample Start Delay from Setting Sample bit (SAMP) 75 -- -- 250 -- -- ns ns TCY = 75 ns, AD1CON3 in default state Conversion Rate AD55 AD56 AD57 AD61 Note 1: tCONV FCNV tSAMP tPSS -- -- -- Clock Parameters 2 -- 3 TAD 12 -- 1 -- 500 -- TAD ksps TAD AVDD > 2.7V Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2010 Microchip Technology Inc. DS39969B-page 385 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 386 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 31.0 31.1 PACKAGING INFORMATION Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 64-Lead QFN (9x9x0.9 mm) PIC24FJ256 DA106-I/ PT e3 1020017 Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) PIC24FJ256 DA206-I/MR e3 1010017 Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC24FJ256DA 110-I/PT e3 1020017 121-BGA (10x10x1.1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC24FJ256DA 110-I/BG e3 1020017 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010 Microchip Technology Inc. DS39969B-page 387 PIC24FJ256DA210 FAMILY 31.2 Package Details [ [ PP %RG\ PP >74)3@ The following sections give the technical details of the packages. /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E 0,1 0,//,0(7(56 120 %6& 5() %6& %6& %6& %6& 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS39969B-page 388 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ 2010 Microchip Technology Inc. DS39969B-page 389 PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 390 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc. DS39969B-page 391 PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 392 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 b N 1 23 NOTE 1 c NOTE 2 A L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E 5() %6& %6& %6& %6& %6& 0,1 A1 L1 0,//,0(7(56 120 0$; A2 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % 2010 Microchip Technology Inc. DS39969B-page 393 PIC24FJ256DA210 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS39969B-page 394 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc. DS39969B-page 395 PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 396 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY APPENDIX A: REVISION HISTORY Revision A (February 2010) Original data sheet for the PIC24FJ256DA210 family of devices. Revision B (May 2010) Minor changes throughout text and the values in Section 30.0 "Electrical Characteristics" were updated. 2010 Microchip Technology Inc. DS39969B-page 397 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 398 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY INDEX A A/D Conversion 10-Bit High-Speed A/D Converter............................. 325 A/D Converter ................................................................... 325 Analog Input Model ................................................... 333 Transfer Function...................................................... 333 AC Characteristics ADC Conversion Timing ........................................... 385 CLKO and I/O Timing................................................ 383 Internal RC Accuracy ................................................ 382 Alternate Interrupt Vector Table (AIVT) .............................. 93 Alternative Master EPMP........................................................................ 273 Assembler MPASM Assembler................................................... 360 Shared I/O Port Structure ......................................... 157 SPI Master, Frame Master Connection .................... 220 SPI Master, Frame Slave Connection ...................... 220 SPI Master/Slave Connection (Enhanced Buffer Modes)................................. 219 SPI Master/Slave Connection (Standard Mode)............................................... 219 SPI Slave, Frame Master Connection ...................... 220 SPI Slave, Frame Slave Connection ........................ 220 SPIx Module (Enhanced Mode)................................ 213 SPIx Module (Standard Mode) ................................. 212 System Clock............................................................ 141 Triple Comparator Module........................................ 335 UART (Simplified)..................................................... 231 USB OTG Device Mode Power Modes.............................. 241 USB OTG Interrupt Funnel ....................................... 248 USB OTG Module..................................................... 240 Watchdog Timer (WDT)............................................ 356 B Block Diagram CRC .......................................................................... 297 Block Diagrams 10-Bit High-Speed A/D Converter............................. 326 16-Bit Asynchronous Timer3 and Timer5 ................. 193 16-Bit Synchronous Timer2 and Timer4 ................... 193 16-Bit Timer1 Module................................................ 189 32-Bit Timer2/3 and Timer4/5 ................................... 192 96 MHz PLL .............................................................. 150 Accessing Program Space Using Table Operations .......................................................... 77 Addressing for Table Registers................................... 81 BDT Mapping for Endpoint Buffering Modes ............ 244 CALL Stack Frame...................................................... 75 Comparator Voltage Reference ................................ 341 CPU Programmer's Model .......................................... 41 CRC Shift Engine Detail............................................ 297 CTMU Connections and Internal Configuration for Capacitance Measurement.......................... 343 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 344 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 344 Data Access From Program Space Address Generation ........................................... 76 Graphics Module Overview....................................... 305 I2C Module ................................................................ 224 Individual Comparator Configurations, CREF = 0 .......................................................... 336 Individual Comparator Configurations, CREF = 1 and CVREFP = 0 ............................. 337 Individual Comparator ConfigurationS, CREF = 1 and CVREFP = 1 ............................. 337 Input Capture ............................................................ 197 On-Chip Regulator Connections ............................... 354 Output Compare (16-Bit Mode)................................. 202 Output Compare (Double-Buffered, 16-Bit PWM Mode) ........................................... 204 PCI24FJ256DA210 Family (General) ......................... 20 PIC24F CPU Core ...................................................... 40 PSV Operation (Higher Word) .................................... 79 PSV Operation (Lower Word) ..................................... 79 Reset System.............................................................. 87 RTCC ........................................................................ 285 C C Compilers MPLAB C18.............................................................. 360 Charge Time Measurement Unit (CTMU)......................... 343 Key Features ............................................................ 343 Charge Time Measurement Unit. See CTMU. Code Examples Basic Sequence for Clock Switching in Assembly .......................................................... 149 Configuring UART1 I/O Input/Output Functions (PPS) ............................................... 168 EDS Read From Program Memory in Assembly ........ 80 EDS Read in Assembly .............................................. 72 EDS Write in Assembly .............................................. 73 Erasing a Program Memory Block (Assembly) ........... 84 I/O Port Read/Write in `C' ......................................... 163 I/O Port Read/Write in Assembly.............................. 163 Initiating a Programming Sequence ........................... 85 PWRSAV Instruction Syntax .................................... 155 Setting the RTCWREN Bit ........................................ 286 Single-Word Flash Programming ............................... 86 Single-Word Flash Programming (`C' Language) .................................................... 86 Code Protection ................................................................ 357 Code Segment Protection ........................................ 357 Configuration Options....................................... 358 Configuration Protection ........................................... 358 Comparator Voltage Reference ........................................ 341 Configuring ............................................................... 341 Configuration Bits ............................................................. 347 Core Features..................................................................... 15 CPU Arithmetic Logic Unit (ALU) ........................................ 43 Control Registers........................................................ 42 Core Registers............................................................ 40 Programmer's Model .................................................. 39 CRC 32-Bit Programmable Cyclic Redundancy Check .......................................... 297 Polynomials .............................................................. 298 Setup Examples for 16 and 32-Bit Polynomials ....... 298 User Interface ........................................................... 298 2010 Microchip Technology Inc. DS39969B-page 399 PIC24FJ256DA210 FAMILY CTMU Measuring Capacitance ............................................ 343 Measuring Time ........................................................ 344 Pulse Delay and Generation ..................................... 344 Customer Change Notification Service ............................. 405 Customer Notification Service........................................... 405 Customer Support ............................................................. 405 F Flash Configuration Words ......................................... 46, 347 Flash Program Memory ...................................................... 81 and Table Instructions ................................................ 81 Enhanced ICSP Operation ......................................... 82 JTAG Operation.......................................................... 82 Programming Algorithm .............................................. 84 RTSP Operation ......................................................... 82 Single-Word Programming ......................................... 86 D Data Memory Address Space............................................................ 47 Memory Map ............................................................... 48 Near Data Space ........................................................ 49 SFR Space.................................................................. 49 Software Stack ............................................................ 75 Space Organization, Alignment .................................. 49 DC Characteristics I/O Pin Input Specifications ....................................... 377 I/O Pin Output Specifications .................................... 378 Program Memory ...................................................... 378 Development Support ....................................................... 359 Device Features 100/121--Pin ............................................................... 19 64-Pin.......................................................................... 18 Doze Mode........................................................................ 156 G Graphics Controller (GFX) ................................................ 305 Key Features ............................................................ 305 Graphics Controller Module (GFX) ................................... 305 Graphics Display Module Display Clock (GCLK) Source .................................. 324 Display Configuration................................................ 324 Memory Locations .................................................... 324 Memory Requirements ............................................. 324 Module Registers...................................................... 306 Graphics Display Module (GFX) ....................................... 305 I I/O Ports Analog Port Pins Configuration................................. 158 Analog/Digital Function of an I/O Pin........................ 158 Input Change Notification ......................................... 163 Open-Drain Configuration......................................... 158 Parallel (PIO) ............................................................ 157 Peripheral Pin Select ................................................ 164 Pull-ups and Pull-downs ........................................... 163 Selectable Input Sources.......................................... 165 I2C Clock Rates .............................................................. 225 Reserved Addresses ................................................ 225 Setting Baud Rate as Bus Master............................. 225 Slave Address Masking ............................................ 225 Idle Mode .......................................................................... 156 Input Capture 32-Bit Mode .............................................................. 198 Operations ................................................................ 198 Synchronous and Trigger Modes.............................. 197 Input Capture with Dedicated Timers ............................... 197 Input Voltage Levels for Port or Pin Tolerated Description Input....................................... 158 Instruction Set Overview................................................................... 365 Summary .................................................................. 363 Instruction-Based Power-Saving Modes................... 155, 156 Interfacing Program and Data Spaces................................ 75 Inter-Integrated Circuit. See I2C. ...................................... 223 Internet Address ............................................................... 405 Interrupt Vector Table (IVT) ................................................ 93 Interrupts Control and Status Registers...................................... 96 Implemented Vectors.................................................. 95 Reset Sequence ......................................................... 93 Setup and Service Procedures ................................. 140 Trap Vectors ............................................................... 94 Vector Table ............................................................... 94 E EDS................................................................................... 273 Electrical Characteristics A/D Specifications ..................................................... 384 Absolute Maximum Ratings ...................................... 371 Capacitive Loading on Output Pin ............................ 380 External Clock Timing ............................................... 381 Idle Current ............................................................... 375 Load Conditions and Requirements for Specifications.................................................... 379 Operating Current ..................................................... 374 PLL Clock Timing Specifications............................... 381 Power-Down Current ................................................ 376 RC Oscillator Start-up Time ...................................... 382 Reset and Brown-out Reset Requirements .............. 382 Temperature and Voltage Specifications .................. 373 Thermal Conditions ................................................... 372 V/F Graph ................................................................. 372 Voltage Regulator Specifications .............................. 379 Enhanced Parallel Master Port. See EPMP...................... 273 ENVREG Pin..................................................................... 354 EPMP ................................................................................ 273 Alternative Master ..................................................... 273 Key Features............................................................. 273 Master Port Pins ....................................................... 274 Equations 16-Bit, 32-Bit CRC Polynomials ................................ 298 A/D Conversion Clock Period ................................... 332 Baud Rate Reload Calculation .................................. 225 Calculating the PWM Period ..................................... 204 Calculation for Maximum PWM Resolution............... 205 Estimating USB Transceiver Current Consumption..................................................... 243 Relationship Between Device and SPI Clock Speed...................................................... 221 RTCC Calibration ...................................................... 294 UART Baud Rate with BRGH = 0 ............................. 232 UART Baud Rate with BRGH = 1 ............................. 232 Errata .................................................................................. 14 J JTAG Interface.................................................................. 358 DS39969B-page 400 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY K Key Features..................................................................... 347 CTMU........................................................................ 343 EPMP........................................................................ 273 RTCC ........................................................................ 285 Program Memory Access Using Table Instructions ................................ 77 Address Construction ................................................. 75 Address Space ........................................................... 45 Flash Configuration Words ......................................... 46 Memory Maps............................................................. 45 Organization ............................................................... 46 Reading From Program Memory Using EDS ............. 78 Pulse-Width Modulation (PWM) Mode.............................. 203 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period.............................................. 204 M Memory Organization.......................................................... 45 Microchip Internet Web Site .............................................. 405 MPLAB ASM30 Assembler, Linker, Librarian ................... 360 MPLAB Integrated Development Environment Software............................................... 359 MPLAB PM3 Device Programmer .................................... 362 MPLAB REAL ICE In-Circuit Emulator System................. 361 MPLINK Object Linker/MPLIB Object Librarian ................ 360 R Reader Response............................................................. 406 Reference Clock Output ................................................... 152 Register Maps A/D Converter............................................................. 61 ANCFG ....................................................................... 64 ANSEL........................................................................ 64 Comparators............................................................... 66 CPU Core ................................................................... 50 CRC............................................................................ 66 CTMU ......................................................................... 62 Enhanced Parallel Master/Slave Port ......................... 65 Graphics ..................................................................... 69 I2CTM........................................................................... 56 ICN ............................................................................. 51 Input Capture.............................................................. 54 Interrupt Controller...................................................... 52 NVM............................................................................ 70 Output Compare ......................................................... 55 Pad Configuration....................................................... 60 Peripheral Pin Select .................................................. 67 PMD............................................................................ 70 PORTA ....................................................................... 58 PORTB ....................................................................... 58 PORTC ....................................................................... 59 PORTD ....................................................................... 59 PORTE ....................................................................... 59 PORTF ....................................................................... 60 PORTG....................................................................... 60 RTCC.......................................................................... 65 SPI.............................................................................. 58 System........................................................................ 70 Timers......................................................................... 53 UART.......................................................................... 57 USB OTG ................................................................... 63 Registers AD1CHS (A/D Input Select)...................................... 330 AD1CON1 (A/D Control 1)........................................ 327 AD1CON2 (A/D Control 2)........................................ 328 AD1CON3 (A/D Control 3)........................................ 329 AD1CSSH (A/D Input Scan Select, High)................. 332 AD1CSSL (A/D Input Scan Select, Low) .................. 331 ALCFGRPT (Alarm Configuration) ........................... 289 ALMINSEC (Alarm Minutes and Seconds Value)..... 293 ALMTHDY (Alarm Month and Day Value) ................ 292 ALWDHR (Alarm Weekday and Hours Value) ......... 293 ANCFG (A/D Band Gap Reference Configuration) ................................................... 331 ANSA (PORTA Analog Function Selection) ............. 159 ANSB (PORTB Analog Function Selection) ............. 160 ANSC (PORTC Analog Function Selection) ............. 160 ANSD (PORTD Analog Function Selection) ............. 161 ANSE (PORTE Analog Function Selection) ............. 161 N Near Data Space ................................................................ 49 O Oscillator Configuration 96 MHz PLL .............................................................. 149 Clock Selection ......................................................... 142 Clock Switching......................................................... 148 Sequence.......................................................... 148 CPU Clocking Scheme ............................................. 142 Display Clock Frequency Division............................. 152 Initial Configuration on POR ..................................... 142 USB Operations ........................................................ 151 Output Compare 32-Bit Mode............................................................... 201 Synchronous and Trigger Modes.............................. 201 Output Compare with Dedicated Timers ........................... 201 P Packaging ......................................................................... 387 Details ....................................................................... 388 Marking ..................................................................... 387 Peripheral Enable Bits ...................................................... 156 Peripheral Module Disable Bits ......................................... 156 Peripheral Pin Select (PPS) .............................................. 164 Available Peripherals and Pins ................................. 164 Configuration Control ................................................ 167 Considerations for Use ............................................. 168 Input Mapping ........................................................... 164 Mapping Exceptions.................................................. 167 Output Mapping ........................................................ 166 Peripheral Priority ..................................................... 164 Registers................................................................... 169 Pin Descriptions 100-Pin Devices............................................................ 8 121 (BGA)-Pin Devices............................................... 11 64-Pin Devices.............................................................. 6 Pin Diagrams 100-Pin TQFP ............................................................... 7 121-Pin BGA ............................................................... 10 64-Pin TQFP/QFN ........................................................ 5 Pinout Descriptions ............................................................. 21 POR and On-Chip Voltage Regulator................................ 354 Power-Saving Clock Frequency and Clock Switching...................... 155 Features.................................................................... 155 Instruction-Based Modes .......................................... 155 Power-up Requirements ................................................... 355 Product Identification System ........................................... 407 2010 Microchip Technology Inc. DS39969B-page 401 PIC24FJ256DA210 FAMILY ANSF (PORTF Analog Function Selection) .............. 162 ANSG (PORTG Analog Function Selection) ............. 162 BDnSTAT Prototype (Buffer Descriptor n Status, CPU Mode) ........................................... 247 BDnSTAT Prototype (Buffer Descriptor n Status, USB Mode) ........................................... 246 CLKDIV (Clock Divider) ............................................ 145 CLKDIV2 (Clock Divider 2) ....................................... 147 CMSTAT (Comparator Status).................................. 339 CMxCON (Comparator x Control) ............................. 338 CORCON (CPU Core Control).............................. 43, 98 CRCCON1 (CRC Control 1) ..................................... 300 CRCCON2 (CRC Control 2) ..................................... 301 CRCDATH (CRC Data High) .................................... 302 CRCDATL (CRC Data Low)...................................... 302 CRCWDATH (CRC Shift High) ................................. 303 CRCWDATL (CRC Shift Low)................................... 303 CRCXORH (CRC XOR High) ................................... 302 CRCXORL (CRC XOR Polynomial, Low Byte) .......................................................... 301 CTMUCON (CTMU Control) ..................................... 345 CTMUICON (CTMU Current Control) ....................... 346 CVRCON (Comparator Voltage Reference Control)............................................ 342 CW1 (Flash Configuration Word 1) ........................... 348 CW2 (Flash Configuration Word 2) ........................... 350 CW3 (Flash Configuration Word 3) ........................... 351 CW4 (Flash Configuration Word 4) ........................... 352 DEVID (Device ID) .................................................... 353 DEVREV (Device Revision) ...................................... 354 G1ACTDA (Active Display Area) .............................. 317 G1CHRX (Character X-Coordinate Print Position).................................................... 321 G1CHRY (Character Y-Coordinate Print Position).................................................... 322 G1CLUT (Color Look-up Table Control) ................... 319 G1CLUTRD (Color Look-up Table Memory Read Data)........................................................ 320 G1CLUTWR (Color Look-up Table Memory Write Data)........................................................ 320 G1CMDH (GPU Command High) ............................. 306 G1CMDL (GPU Command Low)............................... 306 G1CON1 (Display Control 1) .................................... 307 G1CON2 (Display Control 2) .................................... 308 G1CON3 (Display Control 3) .................................... 309 G1DBEN (Data I/O Pad Enable) ............................... 323 G1DBLCON (Display Blanking Control).................... 318 G1DPADRH (Display Buffer Start Address High) ................................................... 315 G1DPADRL (Display Buffer Start Address Low) .................................................... 315 G1DPDPH (Display Buffer Height) ........................... 316 G1DPHT (Display Total Height) ................................ 316 G1DPW (Display Buffer Width) ................................. 315 G1DPWT (Display Total Width) ................................ 316 G1HSYNC (Horizontal Synchronization Control)................................... 317 G1IE (GFX Interrupt Enable) .................................... 311 G1IPU (Inflate Processor Status).............................. 322 G1IR (GFX Interrupt Status) ..................................... 312 G1MRGN (Interrupt Advance) .................................. 321 G1PUH (GPU Work Area Height) ............................. 314 G1PUW (GPU Work Area Width) ............................. 314 G1STAT (Graphics Control Status) .......................... 310 G1VSYNC (Vertical Synchronization Control) .......... 318 G1W1ADRH (GPU Work Area 1 Start Address High) .......................................... 313 G1W1ADRL (GPU Work Area 1 Start Address Low) ........................................... 313 G1W2ADRH (GPU Work Area 2 Start Address High ........................................... 314 G1W2ADRL (GPU Work Area 2 Start Address Low) ........................................... 313 I2CxCON (I2Cx Control) ........................................... 226 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 230 I2CxSTAT (I2Cx Status) ........................................... 228 ICxCON1 (Input Capture x Control 1)....................... 199 ICxCON2 (Input Capture x Control 2)....................... 200 IEC0 (Interrupt Enable Control 0) ............................. 109 IEC1 (Interrupt Enable Control 1) ............................. 110 IEC2 (Interrupt Enable Control 2) ............................. 112 IEC3 (Interrupt Enable Control 3) ............................. 113 IEC4 (Interrupt Enable Control 4) ............................. 114 IEC5 (Interrupt Enable Control 5) ............................. 115 IEC6 (Interrupt Enable Control 6) ............................. 116 IFS0 (Interrupt Flag Status 0) ................................... 101 IFS1 (Interrupt Flag Status 1) ................................... 102 IFS2 (Interrupt Flag Status 2) ................................... 103 IFS3 (Interrupt Flag Status 3) ................................... 105 IFS4 (Interrupt Flag Status 4) ................................... 106 IFS5 (Interrupt Flag Status 5) ................................... 107 IFS6 (Interrupt Flag Status 6) ................................... 108 INTCON1 (Interrupt Control 1).................................... 99 INTCON2 (Interrupt Control 2).................................. 100 INTTREG (Interrupt Controller Test.......................... 139 IPC0 (Interrupt Priority Control 0) ............................. 117 IPC1 (Interrupt Priority Control 1) ............................. 118 IPC10 (Interrupt Priority Control 10) ......................... 127 IPC11 (Interrupt Priority Control 11) ......................... 128 IPC12 (Interrupt Priority Control 12) ......................... 129 IPC13 (Interrupt Priority Control 13) ......................... 130 IPC15 (Interrupt Priority Control 15) ......................... 131 IPC16 (Interrupt Priority Control 16) ......................... 132 IPC18 (Interrupt Priority Control 18) ......................... 133 IPC19 (Interrupt Priority Control 19) ......................... 133 IPC2 (Interrupt Priority Control 2) ............................. 119 IPC20 (Interrupt Priority Control 20) ......................... 134 IPC21 (Interrupt Priority Control 21) ......................... 135 IPC22 (Interrupt Priority Control 22) ......................... 136 IPC23 (Interrupt Priority Control 23) ......................... 137 IPC25 (Interrupt Priority Control 25) ......................... 138 IPC3 (Interrupt Priority Control 3) ............................. 120 IPC4 (Interrupt Priority Control 4) ............................. 121 IPC5 (Interrupt Priority Control 5) ............................. 122 IPC6 (Interrupt Priority Control 6) ............................. 123 IPC7 (Interrupt Priority Control 7) ............................. 124 IPC8 (Interrupt Priority Control 8) ............................. 125 IPC9 (Interrupt Priority Control 9) ............................. 126 IPCn (Interrupt Priority Control 0-23) ........................ 137 MINSEC (RTCC Minutes and Seconds Value)......... 291 MTHDY (RTCC Month and Day Value) .................... 290 NVMCON (Flash Memory Control) ............................. 83 OCxCON1 (Output Compare x Control 1) ................ 206 OCxCON2 (Output Compare x Control 2) ................ 208 OSCCON (Oscillator Control) ................................... 143 DS39969B-page 402 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY OSCTUN (FRC Oscillator Tune)............................... 146 PADCFG1 (Pad Configuration Control) ............ 283, 288 PMCON1 (EPMP Control 1) ..................................... 275 PMCON2 (EPMP Control 2) ..................................... 276 PMCON3 (EPMP Control 3) ..................................... 277 PMCON4 (EPMP Control 4) ..................................... 278 PMCSxBS (Chip Select x Base Address) ................. 280 PMCSxCF (Chip Select x Configuration) .................. 279 PMCSxMD (Chip Select x Mode).............................. 281 PMSTAT (EPMP Status, Slave Mode)...................... 282 RCFGCAL (RTCC Calibration and Configuration).... 287 RCON (Reset Control) ................................................ 88 REFOCON (Reference Oscillator Control) ............... 153 RPINRn (PPS Input) ......................................... 169-179 RPORn (PPS Output) ....................................... 180-187 SPIxCON1 (SPIx Control 1)...................................... 216 SPIxCON2 (SPIx Control 2)...................................... 218 SPIxSTAT (SPIx Status and Control) ....................... 214 SR (ALU STATUS) ............................................... 42, 97 T1CON (Timer1 Control)........................................... 190 TxCON (Timer2 and Timer4 Control)........................ 194 TyCON (Timer3 and Timer5 Control)........................ 195 U1ADDR (USB Address) .......................................... 261 U1CNFG1 (USB Configuration 1) ............................. 262 U1CNFG2 (USB Configuration 2) ............................. 263 U1CON (USB Control, Device Mode) ....................... 259 U1CON (USB Control, Host Mode)........................... 260 U1EIE (USB Error Interrupt Enable) ......................... 270 U1EIR (USB Error Interrupt Status) .......................... 269 U1EPn (USB Endpoint n Control) ............................. 271 U1IE (USB Interrupt Enable)..................................... 268 U1IR (USB Interrupt Status, Device Mode) .............. 266 U1IR (USB Interrupt Status, Host Mode) .................. 267 U1OTGCON (USB OTG Control) ............................. 256 U1OTGIE (USB OTG Interrupt Enable, Host Mode) ....................................................... 265 U1OTGIR (USB OTG Interrupt Status, Host Mode) ....................................................... 264 U1OTGSTAT (USB OTG Status).............................. 255 U1PWMCON USB (VBUS PWM Generator Control) ............................................................. 272 U1PWRC (USB Power Control)................................ 257 U1SOF (USB OTG Start-Of-Token Threshold, Host Mode) ..................................... 262 U1STAT (USB Status) .............................................. 258 U1TOK (USB Token, Host Mode)............................. 261 UxMODE (UARTx Mode).......................................... 234 UxSTA (UARTx Status and Control)......................... 236 WKDYHR (RTCC Weekday and Hours Value)......... 291 YEAR (RTCC Year Value) ........................................ 290 Resets BOR (Brown-out Reset) .............................................. 87 Clock Source Selection............................................... 90 CM (Configuration Mismatch Reset)........................... 87 Delay Times ................................................................ 91 Device Times .............................................................. 90 IOPUWR (Illegal Opcode Reset) ................................ 87 MCLR (Pin Reset)....................................................... 87 POR (Power-on Reset) ............................................... 87 RCON Flags Operation............................................... 89 SFR States.................................................................. 90 SWR (RESET Instruction)........................................... 87 TRAPR (Trap Conflict Reset)...................................... 87 UWR (Uninitialized W Register Reset) ....................... 87 WDT (Watchdog Timer Reset).................................... 87 Revision History................................................................ 397 RTCC Alarm Configuration.................................................. 294 Calibration ................................................................ 294 Key Features ............................................................ 285 Register Mapping ..................................................... 286 S Selective Peripheral Power Control .................................. 156 Serial Peripheral Interface (SPI) ....................................... 211 Serial Peripheral Interface. See SPI. SFR Space ......................................................................... 49 Sleep Mode ...................................................................... 155 Software Simulator (MPLAB SIM) .................................... 361 Software Stack ................................................................... 75 Special Features................................................................. 16 SPI .................................................................................... 211 T Timer1 .............................................................................. 189 Timer2/3 and Timer4/5 ..................................................... 191 Timing Diagrams CLKO and I/O Timing ............................................... 383 External Clock .......................................................... 380 Triple Comparator............................................................. 335 Triple Comparator Module ................................................ 335 U UART ................................................................................ 231 Baud Rate Generator (BRG) .................................... 232 IrDA Support ............................................................. 233 Operation of UxCTS and UxRTS Pins...................... 233 Receiving in 8-Bit or 9-Bit Data Mode ...................... 233 Transmitting Break and Sync Sequence ............................... 233 in 8-Bit Data Mode............................................ 233 Transmitting in 9-Bit Data Mode ............................... 233 Universal Asynchronous Receiver Transmitter. See UART. Universal Serial Bus Buffer Descriptors Assignment in Different Buffering Modes ......... 245 Interrupts and USB Transactions...................................... 249 Universal Serial Bus. See USB OTG. USB On-The-Go (OTG) ...................................................... 16 USB OTG ......................................................................... 239 Buffer Descriptors and BDT...................................... 244 Device Mode Operation............................................ 249 DMA Interface........................................................... 245 Hardware Calculating Transceiver Power Requirements ............ 243 Hardware Configuration............................................ 241 Device Mode..................................................... 241 External Interface ............................................. 243 Host and OTG Modes....................................... 242 VBUS Voltage Generation ................................. 243 Host Mode Operation ............................................... 250 Interrupts .................................................................. 248 Operation.................................................................. 252 Registers .................................................................. 254 VBUS Voltage Generation ......................................... 243 2010 Microchip Technology Inc. DS39969B-page 403 PIC24FJ256DA210 FAMILY V Voltage Regulator (On-Chip)............................................. 354 and BOR ................................................................... 355 Low Voltage Detection .............................................. 354 Standby Mode ........................................................... 355 W Watchdog Timer (WDT).................................................... 355 Control Register........................................................ 356 Windowed Operation ................................................ 356 WWW Address ................................................................. 405 WWW, On-Line Support ..................................................... 14 DS39969B-page 404 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. 2010 Microchip Technology Inc. DS39969B-page 405 PIC24FJ256DA210 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39969B FAX: (______) _________ - _________ Device: PIC24FJ256DA210 Family Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39969B-page 406 2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 DA2 10 T - I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern c) b) Examples: a) PIC24FJ128DA206-I/PT: PIC24F device with Graphics Controller and USB On-The-Go, 128-KB program memory, 96-KB data memory, 64-pin, Industrial temp., TQFP package. PIC24FJ256DA110-I/PT: PIC24F device with Graphics Controller and USB On-The-Go, 256-KB program memory, 24-KB data memory, 100-pin, Industrial temp., TQFP package. PIC24FJ256DA210-I/BG: PIC24F device with Graphics Controller and USB On-The-Go, 256-KB program memory, 96-KB data memory, 121-pin, Industrial temp., BGA package. Architecture Flash Memory Family Product Group 24 FJ = 16-bit modified Harvard without DSP = Flash program memory DA2 = General purpose microcontrollers with Graphics Controller and USB On-The-Go 06 10 I = 64-pin = 100-pin (TQFP)/121-pin (BGA) = -40C to +85C (Industrial) Pin Count Temperature Range Package PT = 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack) PT = 64-lead, TQFP (Thin Quad Flatpack) MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack, No Lead) BG = 121-pin BGA package Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample Pattern 2010 Microchip Technology Inc. DS39969B-page 407 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/05/10 DS39969B-page 408 2010 Microchip Technology Inc. |
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